Staff ASIC Design Engineer

Celero Communications; Irvine (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, a fast-growing start-up in the semiconductor industry, is seeking an ASIC Design Engineer in Irvine, CA. You will play a crucial role in designing and developing ASICs for next-generation optical modems.

The ideal candidate should have a Bachelor’s degree in Electrical Engineering and over 3 years of experience in digital design. Responsibilities include digital circuit design using HDL and collaborating with cross-functional teams on system integration.

Offered salary ranges from $150,000 to $250,000 annually depending on qualifications.

Qualifications

• Bachelor's or higher degree in Electrical Engineering, Computer Engineering, or a related field.
• 3+ years of experience in digital design and verification.
• Proficiency in HDLs such as Verilog or System Verilog.

Responsibilities

• Design and implement digital circuits using HDL (Verilog/System Verilog).
• Perform synthesis, timing analysis, and verification.
• Collaborate with cross-functional teams on system integration.

Skills

Digital Circuit Design

HDL (Verilog/System Verilog)

ASIC Design Flow

Low-Power Design Techniques

Digital Signal Processing

Verification Methodologies (UVM)

Communication Skills

Education

Bachelor’s degree in Electrical Engineering or related field

Tools

ASIC Design Tools

Scripting Languages (Python, Tcl)

Job description

About The Role

Celero Communication Inc. is an exciting and fast-growing start‑up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure.

Celero is seeking skilled and motivated ASIC Design Engineers to join our team and contribute to the development of optical transceivers for next‑generation optical modems. The ideal candidate will play a crucial role in designing and developing ASICs for cutting‑edge technologies.

Locations

Irvine, CA | San Jose, CA | Ottawa, ON, Canada | Vancouver, BC, Canada

Key Responsibilities

• Design and implement digital circuits using HDL (Verilog/ System Verilog).
• Perform synthesis, timing analysis, Lint, formal equivalence, Clock Domain Crossing (CDC) analysis.
• Optimize designs for performance, power, and area (PPA) requirements.
• Perform RTL simulation and verification to ensure design functionality.
• Participate in design reviews and provide technical guidance to team members.
• Collaborate with cross‑functional teams on system integration and validation.

Qualifications

• Bachelor’s or higher degree in Electrical Engineering, Computer Engineering, or a related field.
• 3+ years of experience in digital design and verification.
• Proficiency in HDLs such as Verilog or System Verilog.
• Strong understanding of digital design principles and methodologies.
• Familiarity with ASIC design flow, and experience with ASIC design tools.
• Knowledge of low‑power design techniques.
• Familiarity with verification methodologies (e.g., UVM, formal verification).
• Excellent problem‑solving, strong communication and teamwork skills.

Preferred Skills

• Strong knowledge of Digital Signal Processing (DSP), Digital Communication, and Forward Error Correction (FEC) techniques.
• Experience with scripting languages (e.g., Python, Tcl).
• Understanding of Optical Communication Standards is a plus.
• Ability to multitask and adapt to a fast‑paced, dynamic environment.

Salary Range

$150,000 - $250,000 Base Annually.

The final offer will be determined based on job-related skills, experience, qualifications, and location.