Digital Design Engineer

Xcelerium; Irvine (CA); On-site; USD 130,000 - 160,000; Full time

Job summary

Xcelerium, located in Irvine, CA, is seeking an ASIC RTL Design Engineer to develop high-performance, low-power digital designs and RISC-V cores. You will collaborate with various teams to optimize designs, ensuring quality and efficiency.

This role requires a Bachelor's degree in engineering and over 5 years of experience. A strong understanding of Verilog/SystemVerilog and a passion for technology will be essential for success in this innovative environment.

Qualifications

• 5+ years of relevant professional experience in ASIC design.
• Familiarity with RTL to GDS design flow.
• Passion for learning new technologies.

Responsibilities

• Architect, design, and implement digital designs for ASICs and SoCs.
• Microarchitecture development and specification with collaborative documentation.
• Optimize physical design to meet frequency, area, and power goals.

Skills

Logic design using Verilog/SystemVerilog

Processor architecture knowledge

Strong programming skills in Python, C/C++, or assembly

Education

Bachelor's in Computer Engineering or Electrical Engineering

Job description

Xcelerium is a fabless semiconductor company established in 2020 by experienced team from Qualcomm, Intel and Broadcom. Xcelerium develops silicon and software for sensor processing, communications and latency-sensitive AI applications. Working at Xcelerium will provide an opportunity to work on a complex development from the ground up and become familiar with cutting edge technologies such as RISC-V, digital signal processing, machine learning, many-core parallel processing using CUDA/OpenCL, inner workings of frameworks such as TensorFlow, PyTorch, OpenGL, real-time operating systems and embedded in addition, the application domains will be 5G, UAVs/Drone, Robots, and Autonomous Vehicles which provide enormous scope for growth and making an impact.

Job Summary

As an ASIC RTL Design Engineer, you will work on developing and implementing cutting-edge complex digital designs, SoCs, and industry-leading RISC-V cores. You will collaborate with the RTL design team, firmware team, and physical implementation team to optimize the design for performance, power efficiency, and area.

Key Responsibilities

• Architect, design, and implement high-performance, low-power, and area-efficient digital designs for ASICs and SoCs using industry-standard EDA tools.
• Microarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.
• Work with physical implementation team to implement and optimize physical design to meet frequency, area, power goals.
• Collaborate with performance modelling team for performance exploration and optimization to meet performance goals.

Technical Qualifications

• Bachelor's in Computer Engineering or Electrical Engineering from a reputable institution
• 5+ years of relevant professional experience
• Excellent understanding of logic design using hardware description languages like Verilog/SystemVerilog is required.
• Familiarity with processor architecture, memory and cache subsystems, on-chip interconnects and network-on-chip technology
• Familiarity with either UVM based verification flow
• Familiarity with RTL to GDS design flow is required
• Knowledge of RISC-V architectures is a strong plus
• Strong programming skills in Python, C/C++, Chisel or assembly language is highly desirable
• Experience with fixed point arithmetic and data path design is desirable

Other Requirements

• Passion for learning new technologies
• Taking pride in always producing high quality code and documentation
• Comfortable and willing to work with team members from different disciplines, different levels and across time-zones

Location: on-site in Irvine, CA

Alternate locations: Santa Clara, CA; San Diego, CA