Principal ASIC verification Engineer

Nokia; San Jose (CA); On-site; USD 130,000 - 160,000; Full time

Job summary

A leading telecommunications company in San Jose is seeking a Principal Design Engineer to model complex DSP for communication systems. The successful candidate will have extensive experience in analog/mixed-signal circuitry and familiarity with modeling tools like System-Verilog. Responsibilities include performing functional verification and collaborating with teams to ensure robust designs. This is a critical role in shaping the future of optical networking.

Qualifications

• 12+ years experience for M.S. or 8+ years for Ph.D.
• Experience modeling analog/mixed-signal circuitry.
• Ability to code in System-Verilog and perform .LIB generation.

Responsibilities

• Model circuit blocks and mixed-signal IPs for optimal performance.
• Perform functional verification and timing analysis.
• Collaborate with digital verification team on design robustness.

Skills

Modeling analog/mixed-signal IPs

System-Verilog (WREAL)

CMOS analog/mixed-signal design

Verilog-AMS

Matlab coding

Fluent communication

Education

M.S. in Electrical Engineering or Ph.D.

Job description

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise

Join Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.

The successful candidate shall possess abundant experience in designing complex DSP for communication systems. She/he shall also have decent knowledge in analog/mixed-signal circuitry to perform the modeling and optimization of the overall high-performance front ends for communication SoCs.

Qualifications

Mandatory Knowledge/Skills/Abilities:

• Have prominent tracking record in modeling analog/mixed-signal IPs, including but limited to SERDES, optical links, and wireless transmission systems.
• Hands‑on in modeling and simulating with System‑Verilog (WREAL), Verilog-AMS, and/or C, C++.
• Have a decent understanding in CMOS analog / mixed-signal design.

Preferred Knowledge/Skill/Abilities:

• Able to create IBIS-AMI model.
• Can code in System-Verilog (WREAL).
• Able perform .LIB generation
• Fluent in verbal and written communications;
• Independently resolves issues and conquer design challenges;
• Self‑motivated and detail‑oriented;
• Has the knowledge of (optical) communication theories and Matlab coding.

Education and Experience Requirements:

• Principal Design Engineer: M.S. in E.E. with 12+ years’ experience, or Ph.D. in E.E. with 8+ years’ experience

Responsibilities

• Model the circuit blocks and mixed‑signal IPs, including but not limited to high‑speed ADCs, DACs, CTLE, FFE, and PLLs, to work with the architect and designers to achieve the optimal system‑level performance.
• Perform the functional verification and timing analysis on the IPs and the blocks.
• Work with the digital verification team to generate an adequate interface to ensure the robustness of the design.