Sr. ASIC Design Engineer

HITEC; Roseville, Northern (CA, KY); Hybrid; USD 140.000 - 230.000; Vollzeit

Zusammenfassung

Hewlett Packard Enterprise in California is seeking a Sr. ASIC Design Engineer for a hybrid role requiring on-site ~2 days per week.

You will lead the design of high-speed networking ASICs, from specifications to netlist, with emphasis on Verilog/SystemVerilog, timing closure, and integration with physical design. You will mentor new engineers, collaborate with verification and PD teams, and contribute to architectural decisions.

Qualifikationen

• Bachelor’s degree in Electrical Engineering required; Master’s strongly desired.
• 5+ years of relevant ASIC design experience preferred.
• Proficiency with Verilog/SystemVerilog and EDA flows.

Aufgaben

• Develop functional specifications and micro-architectures for ASIC modules.
• Implement designs using Verilog or SystemVerilog.
• Create functional coverage and assertions (SVA) for verification.
• Collaborate with Physical Design for floorplanning and timing closure.
• Mentor new engineers and interns.

Kenntnisse

Verilog

SystemVerilog

Computer Architecture

Networking protocols

Analytical/problem solving

Leadership/mentoring

Ausbildung

Bachelor’s degree in Electrical Engineering

Master’s degree in Electrical Engineering

Tools

Synthesis tools

Lint tools

Timing analysis

Jobbeschreibung

Sr. ASIC Design Engineer

This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office.

Who We Are:

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.

Job Description:

Job Family Definition:

HPE Networking is a leading provider of advanced routers and switches for the internet. We keep the world connected with speed, reliability, security, and ease of use. At HPE Networking Silicon group, we push the boundaries of what is possible in a piece of silicon die. We build cutting edge networking chips used to build our world-class routers and switches.

Bring your passion and there are no boundaries to what you can accomplish here. We are like a start-up in a big company. Year after year, our group builds the most powerful and highest density networking chips.

As part of our fast-paced silicon group, you will become an expert in building high-speed ASICs, from specifications to final netlist. We give you opportunities to work on complex modules and subsystems where you can challenge yourself and grow.

Open communications, empowerment, innovation, teamwork, and customer success are the foundations of team culture. Thus, you set your own limits for learning, achievements, and rewards.

Responsibilities:

• You will start with a functional specification of a module and produce a detailed micro-architecturespecificationthat meets the power/area requirements.

• You will implement the design using Verilog or System Verilog

• Write functional coverage/SVAto help verification catch corner casebugs.

• You will work withthe PhysicalDesign team foroptimalfloorplan andtiming closure. You willidentifyand fix timing in RTL to meet the frequency target.

• Work with the Verification team to make sure your block is fullyvalidated.

• You will have opportunities to improveleadershipskillsby providingmentoring/guidance to new college-grad engineers andinterns.

Recommended skills

• Bachelor’s degree in Electrical Engineeringrequired(Master’sstronglydesired) with 5+years of relevantexperience.

• Strong analytical/problem solving skills.

• Knowledge of Computer Architecture/networking protocols through graduate level courses orpriorworkis a plus.

• Strong coding skills in Verilog/System Verilog through courses/projects andpreviouswork experienceisdesired.

• Knowledge of synthesis/lintand otherstate-of-the-artEDA toolsisdesired.

• Excellent written and verbalcommunicationsskillsaregood to have.