ASIC Design Engineer II: High-Speed Networking Chips

Hewlett Packard Enterprise; Sunnyvale (CA); On-site; USD 106,000 - 214,000; Full time

Benefits offered by this job

Health & Wellbeing

Personal & Professional Development

Unconditional Inclusion

Job summary

Hewlett Packard Enterprise in Sunnyvale, California, is seeking an ASIC Design Engineer 2 to join our fast-paced chip design group. This onsite role focuses on building high-speed ASICs from specification to netlist, with opportunities to explore design, verification, or timing closure.

You will develop RTL in SystemVerilog, verify functionality, and partner with PD to ensure timing targets are met, while leveraging cutting-edge EDA tools and a culture that values innovation and collaboration.

Qualifications

• Bachelor’s degree in Electrical Engineering is required.
• Strong coding skills in Verilog/SystemVerilog through coursework and projects.
• Experience with RTL coding, timing closure, and PD relationships is beneficial.
• Exposure to digital logic design and computer architecture is a plus.

Responsibilities

• Start with a functional specification and develop micro-architecture for a module.
• RTL coding in SystemVerilog; work with synthesis-ready projects.
• Write functional coverage/SVA; learn to create verification environments.
• Collaborate with PD to identify timing paths and fix RTL to meet frequency targets.
• Debug blocks identified by the verification team; use state-of-the-art EDA tools for checks.

Skills

Verilog

SystemVerilog

RTL coding

Python

Perl

Analytical skills

Communication skills

Digital logic design

Education

Bachelor’s degree in Electrical Engineering

Master’s degree (preferred)

Tools

EDA tools

Job description

Hewlett Packard Enterprise in Sunnyvale, California, is seeking an ASIC Design Engineer 2 to join our fast-paced chip design group. This onsite role focuses on building high-speed ASICs from specification to netlist, with opportunities to explore design, verification, or timing closure.

You will develop RTL in SystemVerilog, verify functionality, and partner with PD to ensure timing targets are met, while leveraging cutting-edge EDA tools and a culture that values innovation and collaboration.