Director, ASIC RTL & Front-End Implementation

Socket.dev; Roseville (CA); On-site; USD 250,000 - 350,000; Full time

Benefits offered by this job

Health & wellbeing programs

Career development programs

Inclusive culture

Job summary

Hewlett Packard Enterprise is seeking a Director of ASIC Design & Front-End Implementation to lead RTL design and tapeout readiness for next-gen networking ASICs. You’ll partner with Architecture, Verification, Emulation, Software, and Product teams to ensure milestones are met while optimizing performance, power and area.

You will manage multidisciplinary teams, drive design reviews, and advance methodologies to enable successful silicon production and market delivery.

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 15+ years of ASIC development experience, including 8+ years leading engineering teams and managers.
• Expertise in RTL design, Verilog/SystemVerilog, microarchitecture development, synthesis, CDC, linting, timing closure, and ASIC implementation flows.
• Proven success delivering complex ASICs from concept through production.
• Strong cross-functional leadership, communication, and program execution skills.

Responsibilities

• Lead RTL design and microarchitecture teams delivering complex networking ASICs.
• Drive design execution from architecture through RTL completion with PPA targets.
• Establish design methodologies, coding standards and best practices.
• Review and approve architectural and implementation trade-offs.
• Partner with Physical Design for floorplanning, timing closure, power optimization, tapeout readiness.
• Ensure RTL designs are production-ready and scalable.

Skills

RTL design

Verilog/SystemVerilog

microarchitecture

synthesis

CDC

linting

timing closure

ASIC implementation

cross-functional leadership

program execution

Education

BS/MS in Electrical Engineering or Computer Engineering

Job description

Hewlett Packard Enterprise is seeking a Director of ASIC Design & Front-End Implementation to lead RTL design and tapeout readiness for next-gen networking ASICs. You’ll partner with Architecture, Verification, Emulation, Software, and Product teams to ensure milestones are met while optimizing performance, power and area.

You will manage multidisciplinary teams, drive design reviews, and advance methodologies to enable successful silicon production and market delivery.