Hybrid ASIC Verification Engineer - Networking

Hewlett Packard Enterprise Company in; Sunnyvale (CA); Hybrid; USD 120,000 - 243,000; Full time

Job summary

Hewlett Packard Enterprise is seeking a highly motivated ASIC Verification Engineer to join the networking silicon development team in Sunnyvale, CA. This hybrid role requires you to be in the office 2 days per week while you drive block-level verification and develop advanced UVM environments.

Responsibilities include test planning, coverage analysis, and debugging of complex SoC designs using Cadence Xcelium, Synopsys VCS, and Mentor Questa.

Qualifications

• 3+ years of experience in ASIC/SoC verification with a proven track record of owning verification from test plan to coverage closure.
• Strong expertise in SystemVerilog and UVM methodology, including developing environments from scratch.
• Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).
• Hands-on experience in test planning, coverage analysis, and debugging of complex SoC designs.
• Proficiency with industry-standard simulation tools (Cadence Xcelium, Synopsys VCS, Mentor Questa) and waveform debugging.

Responsibilities

• Own and drive block-level or subsystem verification efforts, from creating test plans to achieving comprehensive coverage closure.
• Develop, enhance, and maintain advanced UVM verification environments, including agents, sequences, scoreboards, virtual sequences, and register models.
• Perform constraint-driven random testing, debug complex SoC designs, and ensure functional coverage and assertion goals are met.
• Analyze simulation results using industry-leading simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and debug waveforms to validate design functionality.
• Collaborate with cross-functional teams to identify and resolve issues, ensuring high-quality ASIC/SoC deliverables.

Skills

ASIC verification

SystemVerilog

UVM methodology

Test planning

Debugging

Cadence Xcelium

Synopsys VCS

Mentor Questa

Tools

Cadence Xcelium

Synopsys VCS

Mentor Questa

Job description

Hewlett Packard Enterprise is seeking a highly motivated ASIC Verification Engineer to join the networking silicon development team in Sunnyvale, CA. This hybrid role requires you to be in the office 2 days per week while you drive block-level verification and develop advanced UVM environments.

Responsibilities include test planning, coverage analysis, and debugging of complex SoC designs using Cadence Xcelium, Synopsys VCS, and Mentor Questa.