Senior Networking ASIC Verification Engineer

Hewlett Packard Enterprise; Sunnyvale (CA); Hybrid; USD 120,000 - 243,000; Full time

Benefits offered by this job

Health & Wellbeing

Professional Development

Unconditional Inclusion

Job summary

Hewlett Packard Enterprise seeks an ASIC Verification Engineer in Sunnyvale, CA. The role is hybrid, with office presence required 2 days per week. You will lead block-level verification, build advanced UVM environments, and ensure coverage closure for complex networking ASICs.

You will work with Cadence Xcelium, Synopsys VCS, and Mentor Questa, collaborating across teams to deliver high‑quality ASIC/SoC bring‑ups and debug of complex designs.

Qualifications

• 5+ years of experience in ASIC/SoC verification with a proven track record of owning verification from test plan to coverage closure.
• Strong expertise in SystemVerilog and UVM methodology, including developing environments from scratch.
• Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).
• Hands-on experience in test planning, coverage analysis, and debugging of complex SoC designs.
• Proficiency with industry-standard simulation tools (Cadence Xcelium, Synopsys VCS, Mentor Questa) and waveform debugging.

Responsibilities

• Own and drive block-level or subsystem verification efforts, from creating test plans to achieving comprehensive coverage closure.
• Develop, enhance, and maintain advanced UVM verification environments, including agents, sequences, scoreboards, virtual sequences, and register models.
• Perform constraint-driven random testing, debug complex SoC designs, and ensure functional coverage and assertion goals are met.
• Analyze simulation results using industry-leading simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and debug waveforms to validate design functionality.
• Collaborate with cross-functional teams to identify and resolve issues, ensuring high-quality ASIC/SoC deliverables.

Skills

SystemVerilog

UVM

Test planning

Coverage analysis

Debugging

Randomization

Assertions (SVA)

Tools

Cadence Xcelium

Synopsys VCS

Mentor Questa

Job description

Hewlett Packard Enterprise seeks an ASIC Verification Engineer in Sunnyvale, CA. The role is hybrid, with office presence required 2 days per week. You will lead block-level verification, build advanced UVM environments, and ensure coverage closure for complex networking ASICs.

You will work with Cadence Xcelium, Synopsys VCS, and Mentor Questa, collaborating across teams to deliver high‑quality ASIC/SoC bring‑ups and debug of complex designs.