Physical Design Engineer

Indus Valley Consultants, Inc.; San Jose (CA); Hybrid; USD 96,000 - 165,000; Full time

Job summary

Indus Valley Consultants, Inc. is seeking a Physical Design Engineer for a 12-month contract to support timing-critical large-scale designs in San Jose, CA and Austin, TX (Hybrid 3 days onsite). This role focuses on synthesis, floorplanning, and close collaboration with RTL teams.

The ideal candidate has extensive PD experience at advanced technology nodes, with hands-on Cadence Genus and Innovus expertise to drive timing closure and PPA optimization.

Qualifications

• 8+ years of PD experience on large-scale SoC or AI-class designs.
• Hands-on with advanced technology nodes (N5, N3 or below).
• Strong understanding of timing closure and the link between synthesis and implementation.
• Experience with Cadence Genus and Innovus is preferred.

Responsibilities

• Perform synthesis using Cadence Genus for large, timing-challenged designs.
• Drive PPA (power, performance, area) optimization through synthesis and early implementation stages.
• Develop and refine floorplans using Cadence Innovus.
• Collaborate closely with RTL teams to provide timely feedback on design quality, constraints, and architectural tradeoffs.
• Partner with external P&R teams to iterate toward timing closure and PPA optimization.
• Identify and address timing bottlenecks early in the flow to improve convergence.

Skills

Synthesis

Floorplanning

Timing closure

PPA optimization

Cross-functional collaboration

Tools

Cadence Genus

Cadence Innovus

Job description

Title: Physical Design Engineer

Location: San Jose, CA and Austin, TX (Hybrid 3 days Onsite)

Duration: 12 months

Interview: MS Teams

Job Summary

We are seeking a Physical Design contractor with strong synthesis and implementation expertise to support large, timing-critical designs at advanced technology nodes.

Key Responsibilities

• Perform synthesis using Cadence Genus for large, timing-challenged designs
• Drive PPA (power, performance, area) optimization through synthesis and early implementation stages
• Develop and refine floorplans using Cadence Innovus
• Collaborate closely with RTL teams to provide timely feedback on design quality, constraints, and architectural tradeoffs
• Partner with external P&R teams to iterate toward timing closure and PPA optimization
• Identify and address timing bottlenecks early in the flow to improve convergence

Preferred Qualifications

• Proven experience with large-scale SoC or AI-class designs
• At least 8 years of PD experience
• Hands-on experience at advanced / cutting-edge technology nodes (e.g., N5, N3 or below)
• Strong understanding of timing closure and correlation between synthesis and implementation
• Hands-on experience with Cadence Genus and Innovus
• Ability to work cross-functionally with RTL, architecture, PD, and external implementation teams