Analog IC Layout Engineer for DRAM & IP Design

Micron Technology, Inc.; Boise (ID); On-site; USD 110,000 - 170,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Job summary

Micron Technology, Inc. is seeking a layout engineer to design physical IC layouts for memory products in Boise. You will handle analog layout, floor planning, routing, and power distribution, ensuring the layout aligns with schematics and process rules.

You will verify layouts using LVS/DRC/DFM and collaborate with circuit designers across teams in the US, India, and Japan to deliver high-quality layouts on schedule. A Master’s degree in Electrical or Computer Engineering is required.

Qualifications

• Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• Experience with IC layout and IP layout design is required.
• Proficiency with Cadence OA and verification tools (Caliber) is expected.

Responsibilities

• Create physical layout of transistors, resistors, and capacitors for analog circuits used in memory products.
• Perform floor planning, routing, and power bus designs; ensure layout matches schematics.
• Deliver layout and DBR on time; verify with LVS/DRC/DFM and provide documentation.

Skills

DRAM functions

IC layout design

Layout verification

Floor planning & routing

Education

Master’s degree in Electrical/Computer Engineering

Tools

Cadence OA

Caliber verification tools

DRC/LVS workflows

Job description

Micron Technology, Inc. is seeking a layout engineer to design physical IC layouts for memory products in Boise. You will handle analog layout, floor planning, routing, and power distribution, ensuring the layout aligns with schematics and process rules.

You will verify layouts using LVS/DRC/DFM and collaborate with circuit designers across teams in the US, India, and Japan to deliver high-quality layouts on schedule. A Master’s degree in Electrical or Computer Engineering is required.