Analog IC Layout & Verification Engineer

Micron Technology, Inc.; Boise (ID); On-site; USD 90,000 - 120,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time-off and holidays

Affirmative benefits programs

Job summary

Micron Technology, Inc. in Boise, Idaho is seeking a layout engineer for analog and IP layout design of memory products. You will perform floor planning, routing, DRC/LVS checks, and ensure layout matches schematics, collaborating with teams in US, India, and Japan.

Requires a Master's degree in Electrical or Computer Engineering or related field, with experience in Cadence OA/Caliber tooling and IP layout design.

Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, or related field.
• Experience with IC layout for IP layout design.
• Knowledge of Cadence OA and Caliber verification tools.
• Familiarity with DRC/LVS and layout-pattern making.

Responsibilities

• Create physical layout for transistors, resistors, and capacitors in memory products.
• Perform floor planning, routing, and power bus designs and verify against schematics.
• Deliver layout and DBR on time with quality checks (LVS/DRC/DFM).
• Coordinate with design teams across the US, India, and Japan.

Skills

DRAM circuits

IP layout design

Layout verification

DRC/LVS

Floor planning

Education

Master's degree in Electrical or Computer Engineering or related field

Tools

Cadence OA

Caliber verification

Job description

Micron Technology, Inc. in Boise, Idaho is seeking a layout engineer for analog and IP layout design of memory products. You will perform floor planning, routing, DRC/LVS checks, and ensure layout matches schematics, collaborating with teams in US, India, and Japan.

Requires a Master's degree in Electrical or Computer Engineering or related field, with experience in Cadence OA/Caliber tooling and IP layout design.