Design Verification Engineer

Platform Recruitment; San Francisco (CA); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Equity

Full benefits

Job summary

Platform Recruitment is seeking verification engineers for a well-funded AI infrastructure startup building high-performance silicon for GenAI in San Francisco. Openings span all levels and emphasize moving between core verification and tooling.

You will shape verification methodology, develop scalable testbenches, and drive sign-off reviews toward milestones including tapeout. This role requires experience from architecture through production silicon and strong SystemVerilog, Python, and C/C++

Qualifications

• Concept-to-silicon experience from an architecture or design spec through to production silicon.
• Proficiency in SystemVerilog, Python and C/C++ for verification and silicon modelling.
• Experience with production verification flows, including testbenches, tests and coverage artifacts.

Responsibilities

• Shape the verification methodology, building a scalable approach across block, subsystem, full-chip and system-level validation
• Own verification execution at subsystem and chip level, building tests and artifacts to close coverage
• Plan and drive verification reviews (test plans, progress, closure) toward milestones including tapeout
• Work from architecture and design specifications through to production silicon

Skills

SystemVerilog

Python

C/C++

UVM

Formal verification

Simulation

Tools

SystemVerilog

Python

C/C++

UVM

Formal verification

Job description

We're working with a well-funded, highly selective AI infrastructure startup building silicon for large-scale AI inference and training. Founded by veteran chip architects who previously led a major AI hardware program at a top tech company, the business has grown fast and is backed by top-tier investors.

They're looking for verification engineers to help build best-in-class silicon for high-performance, sustainable GenAI, across compute, memory management, and high-speed connectivity. They have openings at all levels.

Scope isn't fixed here: they want versatile engineers who can move between core verification and tooling rather than staying in one lane.

Responsibilities

• Shape the verification methodology, building a scalable approach across block, subsystem, full-chip and system-level validation
• Own verification execution at subsystem and chip level, building the testbenches, tests and artifacts needed to close structural and functional coverage
• Plan and drive verification reviews (test plans, execution progress, closure), both intermediate and sign-off, towards milestones including design freeze and tapeout
• Work from architecture and design specifications through to production silicon

Requirements

• Concept-to-silicon experience: you've driven verification from an architecture or design spec through to production silicon
• Working knowledge of SystemVerilog, Python and C/C++ for verification and silicon modelling
• Production experience with UVM and assertion-based verification, and comfort with both formal and simulation-based verification
• Production experience building portable tests and drivers that carry over into silicon validation and post-silicon debug
• Strong grasp of micro-architecture and design concepts in high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity and memory management

Nice to Have

• Familiarity with emulation and prototyping platforms and methodologies
• Hands-on participation in silicon debug and bring-up

What Sets This Role Apart

• Real mission: an AI silicon company building best-in-class, power-efficient chips for GenAI, spanning compute, memory management and high-speed connectivity
• Scope from block to system: you're not confined to one level of the stack, and you'll see verification through to tapeout
• Ownership: you take real responsibility for subsystem and chip-level verification, and help define the methodology

Package & Process

Compensation is highly competitive, with strong equity and full benefits.