Lead AI Accelerator Verification Engineer

Acceler8 Talent; Mountain View (CA); On-site; USD 200,000 - 350,000; Full time

Job description

Senior Design Verification Engineer

Mountain View, CA – Onsite

$200k–$350k base + equity

We’re working with an early-stage AI compute company developing a full-stack platform built around system-on-wafer architecture and advanced 3D integration. The aim is to reduce the power, latency and infrastructure costs associated with moving data across conventional AI clusters.

The technical work spans silicon, hardware systems, firmware, compilers and kernels, with verification engineers working closely with hardware and software teams.

They’re hiring a Senior Design Verification Engineer to own a verification domain within their AI accelerator program, taking responsibility for strategy, execution and functional closure. This is a senior individual-contributor role with scope across complex IP, subsystems and full-chip verification.

The role

• Own a verification domain, from understanding specifications and developing the verification plan through debug and functional closure.
• Develop end-to-end verification strategies spanning IP, SoC-level testing and emulation.
• Build and maintain UVM testbench architecture suited to complex accelerator designs.
• Work closely with hardware and software engineers to understand system behaviour, identify verification gaps and resolve failures.

Your experience

• At least five years of pre-silicon verification experience, with clear ownership of complex IP, subsystems or SoCs from planning through functional closure.
• Strong experience in one or more relevant domains: block or subsystem verification, CPU subsystem and IP integration, full-chip verification, emulation, DMA/NoC, or multi-SoC and die-to-die protocols.
• Strong command of UVM methodology and testbench architecture.
• A track record of debugging complex designs and delivering end-to-end verification results.
• The ability to interpret specifications from both hardware and software perspectives.

RISC-V, formal verification, emulation platforms such as Palladium or Veloce, and post-silicon bring-up experience would be useful but are not essential.

Why join?

You’ll take ownership of a substantial verification domain on a new AI computing platform, with direct access to the engineers shaping its hardware and software architecture.

The role offers scope to influence verification strategy, testbench design and tooling within a growing team. You’ll also help establish how AI-assisted methods are applied to practical verification and emulation work.

This is an opportunity for someone who wants technical ownership, complex verification problems and a close connection between their work and the delivery of accelerator silicon.

Visa sponsorship and immigration support are available for qualified candidates.