AI Accelerator Physical Design Engineer - Full Time

RosaicLabs Inc; Santa Clara (CA); On-site; USD 150,000 - 230,000; Full time

Benefits offered by this job

Medical insurance

Dental

Vision

Life & AD&D

401(k)

Job summary

RosaicLabs Inc in Santa Clara, CA is seeking an experienced physical design engineer to own the implementation of accelerator blocks and top level, including synthesis, floorplanning, place-and-route, and clock-tree synthesis.

You will collaborate with architecture, RTL, DFT, and verification teams to optimize for power, timing, and area, and you will develop automation for flows, QoR tracking, and silicon bring-up support.

Qualifications

• Experience in high-performance digital design with synthesis and place-and-route.
• Familiarity with timing closure and multi-corner/multi-mode analysis.
• Experience delivering signoff at advanced process nodes and DRC/LVS knowledge.

Responsibilities

• Own physical implementation of accelerator blocks and top level: synthesis, floorplanning, power planning, placement, clock tree synthesis, and routing.
• Develop floorplans for repeated compute tiles, large SRAM arrays, and high-bandwidth data movement, balancing congestion, wire length, and utilization.
• Close timing, power, and area (PPA) targets, including optimization of datapath-heavy and high-fanout structures.
• Manage power delivery and density: power grid design, IR-drop and electromigration analysis, and thermal-aware implementation.
• Implement low-power techniques such as clock gating, power gating, multi-Vt, and multi-voltage domains.
• Run static timing analysis, signal-integrity, and physical verification (DRC/LVS) signoff across corners and modes.
• Partition and implement hierarchical designs, including budgeting and integration of replicated blocks.
• Work with architecture, RTL, DFT, and verification teams to co-optimize design for physical implementability.
• Develop and maintain automation for flows, regressions, and QoR tracking.
• Support silicon bring-up and correlate post-silicon results with pre-silicon predictions.

Skills

Synthesis

Place & Route

Timing Closure

Power Integrity

Scripting: Tcl/Python/Perl

Debugging

RTL Collaboration

Education

Bachelor's or Master's in ECE/CE

Tools

EDA tools

Job description

• Own physical implementation of accelerator blocks and top level: synthesis, floorplanning, power planning, placement, clock tree synthesis, and routing
• Develop floorplans for repeated compute tiles, large SRAM arrays, and high-bandwidth data movement, balancing congestion, wire length, and utilization
• Close timing, power, and area (PPA) targets, including optimization of datapath-heavy and high-fanout structures
• Manage power delivery and density: power grid design, IR-drop and electromigration analysis, and thermal-aware implementation
• Implement low-power techniques such as clock gating, power gating, multi-Vt, and multi-voltage domains
• Run static timing analysis, signal-integrity, and physical verification (DRC/LVS) signoff across corners and modes
• Partition and implement hierarchical designs, including budgeting and integration of replicated blocks
• Work with architecture, RTL, DFT, and verification teams to co-optimize design for physical implementability
• Develop and maintain automation for flows, regressions, and QoR tracking
• Support silicon bring-up and correlate post-silicon results with pre-silicon predictions

What you'll do

• Own physical implementation of accelerator blocks and top level: synthesis, floorplanning, power planning, placement, clock tree synthesis, and routing
• Develop floorplans for repeated compute tiles, large SRAM arrays, and high-bandwidth data movement, balancing congestion, wire length, and utilization
• Close timing, power, and area (PPA) targets, including optimization of datapath-heavy and high-fanout structures
• Manage power delivery and density: power grid design, IR-drop and electromigration analysis, and thermal-aware implementation
• Implement low-power techniques such as clock gating, power gating, multi-Vt, and multi-voltage domains
• Run static timing analysis, signal-integrity, and physical verification (DRC/LVS) signoff across corners and modes
• Partition and implement hierarchical designs, including budgeting and integration of replicated blocks
• Work with architecture, RTL, DFT, and verification teams to co-optimize design for physical implementability
• Develop and maintain automation for flows, regressions, and QoR tracking
• Support silicon bring-up and correlate post-silicon results with pre-silicon predictions

What we're looking for

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
• 5+ years of industry experience in high performance, low power physical design
• Hands-on experience taking complex digital designs through synthesis, place-and-route, and signoff at advanced process nodes
• Strong understanding of timing closure, clocking, and static timing analysis, including OCV and multi-corner multi-mode analysis
• Experience with power integrity: power grid design, IR drop, and electromigration
• Experience with physical verification (DRC/LVS) and fixing violations
• Familiarity with accelerator or compute-array architectures, such as systolic arrays, SIMD/vector engines, and large on-chip memories
• Proficiency with industry-standard EDA tools (see Tools & Technologies)
• Scripting skills in Tcl, Python, or Perl for flow automation
• Strong debugging skills and the ability to work with RTL, architecture, and DFT teams

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

Benefits: Medical (including HSA plans), Dental, Vision, Employee Life & AD&D, 401(k)