ASIC Architect for Energy-Efficient AI Accelerators

Normal Computing Corp.; Mountain View, Northern (CA, KY); Hybrid; USD 180,000 - 260,000; Full time

Job summary

Normal Computing is seeking a Hardware ASIC Architect to define silicon and system microarchitecture for a novel AI accelerator platform. You will drive architectural trade-offs to achieve a 100–1000x energy efficiency leap for LLM and diffusion model inference.

You will lead hardware/software co-design, translate transformer and diffusion workloads into custom compute tiles, and work with RTL, compiler, and analog teams to maximize performance per watt on real workloads.

Qualifications

• A degree in Electrical Engineering, Computer Engineering, or Computer Science; PhD welcome but not required.
• Extensive experience in architecture or microarchitecture of high-performance digital systems (AI accelerators, compute engines).
• Ability to translate workload profiles into datapath widths, pipelines, and power estimates.

Responsibilities

• Define architecture and microarchitecture of AI accelerator compute blocks.
• Translate workload analyses into hardware specifications for RTL teams.
• Defend full-stack PPA tradeoffs across algorithm, memory, interconnect, and physical design.

Skills

AI accelerator arch

RTL/Verilog

Performance modeling

Python/C++

Quantization

Microarchitecture specs

PPA tradeoffs

Workload translation

Simulation tools

SystemVerilog

Education

Electrical Engineering/CS degree

Tools

SystemVerilog

RTL design

RTL tools

Job description

Normal Computing is seeking a Hardware ASIC Architect to define silicon and system microarchitecture for a novel AI accelerator platform. You will drive architectural trade-offs to achieve a 100–1000x energy efficiency leap for LLM and diffusion model inference.

You will lead hardware/software co-design, translate transformer and diffusion workloads into custom compute tiles, and work with RTL, compiler, and analog teams to maximize performance per watt on real workloads.