Advanced ASIC DTCO & Timing Engineer (5nm+)

Qualcomm; San Diego (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking a DTCO and Timing Engineer to analyze DTCO and perform timing studies for Mobile, Compute, Automotive and IoT targets. You will evaluate PPAY for SOCs at block/IP and system levels across 5nm to 2nm processes.

You will run Spice simulations for power/ performance validation, sign-off, and drive PPAY optimization with foundry and CAD teams, contributing to design convergence and production bring-up.

Qualifications

• Bachelor's, Master's, or PhD with 2–4+ years in ASIC design/verification/validation.
• Experience in DTCO analysis and timing for advanced process nodes.
• Proficiency in Python, Perl, TCL, Unix shell, and C/C++ is expected.
• Familiarity with EDA tools and standard RTL-to-GDS flows for hard macros.

Responsibilities

• Perform DTCO analysis for SOC products across 5nm to 2nm processes.
• Conduct Spice simulations (Hspice/Finesim/PrimeSim/AFS/Spectre) for power and performance validation and STA sign-off.
• Lead RTL-to-GDS flow for block-level PPA analysis and hard macro implementation.
• Collaborate with foundry DTCO, EDA partners, CAD and IP teams to optimize Fmax, PPAY and costs.
• Contribute to design convergence improvements and support new process technologies bring-up.
• Develop automation using Python, Perl, TCL, and C/C++ to streamline flows.

Skills

Python

Perl

TCL

Unix shell

C/C++

ML modeling

Education

Bachelor's degree in Science, Engineering, or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Tools

FC Synthesis

FC Place and Route

Genus

Innovus

Hspice

Finesim

PrimeSim

AFS

Spectre

Job description

Qualcomm Technologies, Inc. is seeking a DTCO and Timing Engineer to analyze DTCO and perform timing studies for Mobile, Compute, Automotive and IoT targets. You will evaluate PPAY for SOCs at block/IP and system levels across 5nm to 2nm processes.

You will run Spice simulations for power/ performance validation, sign-off, and drive PPAY optimization with foundry and CAD teams, contributing to design convergence and production bring-up.