Implementation Timing / STA Design Engineer

Qualcomm; San Diego (CA); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Competitive annual discretionary bonus program

Opportunity for annual RSU grants

Comprehensive benefits package

Job summary

Qualcomm is seeking skilled engineers to join its SoC Implementation Team in San Diego, California, focusing on timing constraints development, power analysis, and static timing analysis for premium-tier chips.

The ideal candidate will have a relevant degree and at least 2 years of experience. The position offers a pay range of $140,000.00 to $210,000.00, alongside a competitive benefits package.

Qualifications

• 4+ years of ASIC design, verification, validation, integration, or related work experience.
• 3+ years of ASIC design, verification, validation, integration, or related work experience for Master's.
• 2+ years of ASIC design, verification, validation, integration, or related work experience for PhD.

Responsibilities

• Develop constraints for physical power-aware synthesis and signoff with static timing analysis.
• Collaborate with design teams to identify timing requirements and bottlenecks.
• Generate and validate clock domain crossing and design constraints for timing closure.

Skills

Timing constraints development

Power analysis

Static timing analysis (STA)

Proficient with Primetime

Scripting skills in Tcl

Scripting skills in Perl

Scripting skills in Python

Education

Bachelor's degree in Science, Engineering, or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Job description

Overview

Qualcomm Technologies, Inc. is a leading technology innovator pushing the boundaries of what's possible to enable next-generation experiences and drive communication and data processing transformation to help create a smarter, connected future for all.

The Qualcomm's SoC Implementation Team is looking for skilled engineers to focus on timing constraints development, power analysis, static timing analysis (STA), and timing closure for premium-tier chips. This is an excellent opportunity to join the Snapdragon implementation team, which is responsible for SoCs in sub-3nm nodes across mobile, AI, and automotive sectors. Candidates should have at least 2 years of experience and be proficient with tools such as Primetime, Fishtail/TCM. Scripting skills in Tcl, Perl, or Python are also desirable.

Principal Duties and Responsibilities

• Develop constraints for physical power-aware synthesis, setup for various modes/corners and low-power multi-voltage domain crossings, and signoff with static timing analysis.
• Collaborate closely with RTL design and physical design teams to identify timing requirements and bottlenecks.
• Generate, review, and validate clock domain crossing and design constraints to achieve timing closure of complex SoC cores.
• Review and integrate HM constraints into SoC and ensure correlation between HM and SoC timing.
• Analyze timing across modes and corners, understand concepts like path pessimism and margins.

Minimum Qualifications

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Pay and Benefits

Pay range: $140,000.00 - $210,000.00.

In addition to a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for the annual bonus), Qualcomm offers a highly competitive benefits package designed to support your success at work, at home, and at play.

EEO Statement

Qualcomm is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.