Test Engineering Technical Lead (SMTS)

ADVANCED MICRO DEVICES (SINGAPORE) PTE LTD; Singapore; On-site; SGD 80,000 - 120,000; Full time

Job summary

A leading semiconductor company in Singapore is seeking a Technical Lead to oversee test solutions for next-generation products. The role involves collaboration with various teams to enhance product quality and performance. Ideal candidates will have strong technical leadership, problem-solving skills, and experience in the Semiconductor industry. Knowledge of Python, Java, and test methodologies is essential. This is an opportunity for growth into management in the near future.

Qualifications

• Extensive background in Semiconductor Industry.
• Technical knowledge in DFT and ATE test methodologies.
• Test lead experience in multiple product cycles.

Responsibilities

• Develop characterization and test coverage strategies.
• Optimize product margin for business requirements.
• Interface with global teams on root cause resolutions.

Skills

Technical leadership

Problem solving

Troubleshooting

Effective communication

Market awareness

Multi-tasking

Education

Bachelor's/Master's in Electrical/Electronic Engineering

Tools

Python

Java

Perl

C++

Advantest 93k

Mentor EDA tools

Synopsys EDA tools

Cadence EDA tools

Job description

THE ROLE

The Technical Lead is responsible for the test solution for a next-generation AMD Products. This position serves as the Test Engineering team's Technical Leader and go-to expert for solutions. This position requires engagement with Product, Design, Platform Engineering, Device Analysis, Foundry, Quality and Reliability Engineering to drive test and characterization plan, 1st silicon bring-up, silicon debug, attainment and optimization of yield and performance distributions, test costs and product quality for next-generation AMD products.

THE PERSON

The type of person we are looking for is one with a passion towards technical development, possesses broad technical leadership, critical problem solving and troubleshooting skills. The person must be a team player and have good and effective communications to deep dive into technical discussion with other members across the globe and use data to illustrate their points.

This person is expected to be independent, self‑starter, well organized and have the sense of responsibility to see projects through beginning to the end. This person is expected to be market savvy and comfortable in a multi‑tasking environment.

KEY RESPONSIBILITIES

Key responsibilities for this role will differ according to the product life cycle and are as below:

New product introduction phase:

• Developing characterization and test coverage strategies/plans during pre-silicon phase
• Establishing pattern requirements and driving Design Verification deliveries during pre-silicon phase
• Executing the defined characterization and test plans on new silicon
• Delivery of optimized test and product definitions across PVT corners to meet business requirements.
• Perform new device characterization, circuit sensitivity analysis, interpret findings, guide deep‑dive investigations to root‑cause, and/or provide mitigation actions.
• Interface with global teams across the organization on root cause resolution for device failures.
• Foster and develop new ideas/concepts in device test/debug/DFT/DFM and follow‑through to deliverable outcomes.

Product health and cost target attainment during production phase:

• Optimize test contents to meet/exceed business goal
• Lead effort to optimize product margin to meet business requirements, from Fab to Back‑end‑Test.

PREFERRED EXPERIENCE

• Extensive background and experience in the Semiconductor industry
• Experience must include technical and specialized knowledge in the areas below:
• Strong DFT and ATE test methodologies
• Test lead experience of more than 1 full product cycle is preferred
• ATPG Scan / MBIST / Functional / High speed IO / AMS pattern development and debug experience
• Strong ATE & test class/method development experience with Advantest 93k preferred
• CPU/GPU/APU/DPU/NPU/AI architecture and ASIC/System‑on‑chip (SOC) knowledge
• Strong Python/Java/Perl/C++ coding skills
• Experience with Mentor or Synopsys or Cadence EDA tools or System Level Testing a plus
• Possess of potential and career development plan to Test Manager role in 18~24 months time

ACADEMIC CREDENTIALS

• Bachelors/Masters in Electrical/Electronic Engineering

LOCATION

Singapore