Senior NPI Wafer Bumping & Fan-Out Process Engineer

Lumilens; Singapore; On-site; SGD 90,000 - 135,000; Full time

Job summary

Lumilens seeks an experienced engineer to lead wafer bumping and fan-out process development for silicon photonic wafers. You will design and optimize early-stage flows, run DOEs to map process windows, and drive material evaluations including dielectrics and solder alloys.

You will apply reliability plans (TCT, HAST, HTS), perform root-cause analyses, and develop SOPs and WIs for NPI. Strong background in photolithography and PVD/CVD is required.

Qualifications

• Education: Bachelor or Master degree in Materials Science, Chemical Engineering, Mechanical Engineering, Microelectronics, or equivalent.
• Experience: 5+ years hands-on wafer bumping or Fan-out process integration/development, at OSAT or IDM line.
• Deep understanding of photolithography, wet etching, CVD, and PVD.
• Strong knowledge of FPVA/WLCSP techno-mechanisms and process validation methodologies (FMEA, SPC).
• Proficient in statistical tools: JMP, Minitab, Python.

Responsibilities

• Lead process development and technical support for wafer bumping and Fan-Out for silicon photonic chip wafers.
• Design and optimize early-stage process flows; DOE to characterize process window and margin.
• Evaluate and qualify new materials including dielectric photoresists and solder alloys.
• Design DOE plans for reliability: TCT, HAST, HTS; perform root-cause analyses.
• Compile SOPs, work instructions, and change documents; support NPI validation.

Skills

Wafer bumping

Fan-out integration

DOE

Process optimization

SPC

FMEA

8D problem solving

Photolithography

CVD

PVD

Warpage analysis

Finite element

Python

JMP

Minitab

Education

Materials Science

Chemical Engineering

Mechanical Engineering

Microelectronics

Tools

SEM

CSAM

Python

JMP

Minitab

Job description

Lumilens seeks an experienced engineer to lead wafer bumping and fan-out process development for silicon photonic wafers. You will design and optimize early-stage flows, run DOEs to map process windows, and drive material evaluations including dielectrics and solder alloys.

You will apply reliability plans (TCT, HAST, HTS), perform root-cause analyses, and develop SOPs and WIs for NPI. Strong background in photolithography and PVD/CVD is required.