Senior Wafer Bumping & NPI Process Innovator

Lumilens Inc.; Singapore; On-site; SGD 90,000 - 150,000; Full time

Job summary

Lumilens Inc. in Singapore is seeking an experienced Process Engineer to lead wafer bumping and Fan-Out process development for silicon photonic chip wafers. You will design and optimize early-stage flows, perform DOE, and drive process reliability and yield improvements.

The role requires a strong background in materials science or microelectronics, 5+ years in advanced packaging, and hands-on experience with interposers and 2.5D/3D integration, with a focus on quality and process control.

Qualifications

• Bachelor or Master in Materials Science, Chemical Engineering, Mechanical Engineering or Microelectronics.
• 5+ years hands-on wafer bumping or Fan-Out process integration experience.
• Experience with interposer, 2.5D/3D packaging and related wafer-on-substrate concepts.

Responsibilities

• Lead process development and technical support for wafer bumping and Fan-Out for silicon photonic wafers.
• Design and optimize early-stage process flows including lithography, sputtering, electroplating, and ball drop.
• DOE to characterize process window and margin; drive yield improvements.
• Evaluate materials such as dielectric photoresists, plating chemistries, underfills, and solder alloys.
• Plan and execute reliability tests (TCT, HAST, HTS) and conduct stress analyses.
• Own root-cause analysis for failures (RDL cracking, bump issues) using SEM and CSAM.
• Optimize bumping parameters and monitor process variation with SPC control plans.
• Document SOPs, WIs, failure reports, and support NPI/process verification.

Skills

Wafer bumping

Fan-out packaging

DOE

Process optimization

Statistical analysis

Interposer & 2.5D/3D exposure

Reliability testing

SEM & CSAM instrumentation

Education

Bachelor or Master in Materials Science

Chemical Engineering

Mechanical Engineering

Microelectronics

Tools

SEM

CSAM

Cross-sectioning

Job description

Lumilens Inc. in Singapore is seeking an experienced Process Engineer to lead wafer bumping and Fan-Out process development for silicon photonic chip wafers. You will design and optimize early-stage flows, perform DOE, and drive process reliability and yield improvements.

The role requires a strong background in materials science or microelectronics, 5+ years in advanced packaging, and hands-on experience with interposers and 2.5D/3D integration, with a focus on quality and process control.