Senior Silicon Design & DFT Verification Engineer (Hybrid)

Advanced Micro Devices; Singapore; On-site; SGD 100,000 - 145,000; Full time

Benefits offered by this job

AMD benefits

Job summary

AMD in Singapore seeks an adaptive, self-motivated design verification engineer to join our growing team. You will drive verification for next-gen SERDES IPs and SOCs, delivering high-quality patterns and ensuring testability across multi-site projects.

The role emphasizes collaboration with product test teams, hardware engineers, and design teams, focusing on improving scan architecture, ATPG, timing and power closure while maintaining performance.

Qualifications

• Passion for modern, complex processor architecture and verification.
• Strong communication and collaboration with global teams.
• Analytical mindset and problem-solving abilities.

Responsibilities

• Own generation, validation, and delivery of scan test patterns for SERDES IPs and SOCs.
• Collaborate with product test teams during bring-up and troubleshoot issues.
• Improve scan architecture, coverage, test models, and overall quality.
• Perform ATPG pattern and gate-level netlist analysis to resolve issues.
• Collaborate with physical design engineers to support design closure.
• Address DFT requirements for high-frequency Phy IP designs while minimizing impact.
• Resolve complex interactions between IP and SoC design environments across teams.
• Develop improvements that simplify design complexity and strengthen quality.

Skills

Team collaboration

Excellent communication

Analytical thinking

Problem solving

Adaptability

Education

Bachelor's or Master's in Computer Engineering or Electrical Engineering

Tools

Tessent flows

ATPG tools

IEEE 1149.1 boundary scan

Job description

AMD in Singapore seeks an adaptive, self-motivated design verification engineer to join our growing team. You will drive verification for next-gen SERDES IPs and SOCs, delivering high-quality patterns and ensuring testability across multi-site projects.

The role emphasizes collaboration with product test teams, hardware engineers, and design teams, focusing on improving scan architecture, ATPG, timing and power closure while maintaining performance.