Senior Silicon Design Engineer - DFT

AMD; Singapore; Hybrid; SGD 90,000 - 170,000; Full time

Job summary

AMD is seeking an adaptive design verification engineer to join a global team delivering high-quality, industry-leading technology. You will own the generation and validation of scan test patterns for next-generation SERDES IPs and SOCs, partnering with product test teams to troubleshoot pattern issues and improve coverage.

You’ll work with physical design to support timing, clock-domain, and power analyses while addressing high-frequency DFT requirements.

Qualifications

• Experience with design-for-test methodologies, scan test, and ATPG flow.
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Responsibilities

• Own generation, validation and delivery of scan test patterns for SERDES IPs and SOCs.
• Partner with test teams during bring-up and troubleshoot pattern issues.
• Improve scan architecture, coverage, and test models.
• Perform ATPG pattern and gate-level netlist analysis to resolve issues.
• Collaborate with physical design to support design closure and timing.
• Address DFT requirements for high-frequency Phy IP designs.
• Resolve complex interactions across global teams.
• Develop improvements to simplify design complexity and strengthen engineering quality.

Skills

Scan Test

ATPG

Tessent

Pattern Generation

Multi-clock Domain

Education

Bachelors or Masters degree in computer engineering/Electrical Engineering

Tools

IEEE 1149.1

IEEE 1500

Tessent flows

ATPG debugging

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

THE ROLE:

We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

• Own the generation, validation, and delivery of scan test patterns for next-generation SERDES IPs and SOCs.
• Partner with product test teams during test bring-up and troubleshoot pattern, model, and netlist issues.
• Improve scan architecture, scan coverage, test models, execution methods, and overall product quality.
• Perform ATPG pattern and gate-level netlist analysis to identify and resolve testability and coverage issues.
• Collaborate with physical design engineers to support design closure through static timing, clock-domain crossing, netlist, and power analysis.
• Address DFT requirements for high-frequency Phy IP designs while minimizing performance impact.
• Resolve complex interactions between intellectual property and system-on-chip design environments across global teams.
• Develop and implement improvements that simplify design complexity and strengthen engineering quality.

PREFERRED EXPERIENCE:

• Experience with design-for-test methodologies, particularly scan test and automatic test pattern generation with Tessent flows.
• Strong working knowledge of industry-standard ATPG tools and their application to pattern generation, fault coverage, and product quality.
• Experience debugging ATPG patterns, scan structures, test models, and gate-level netlists.
• Understanding of IEEE 1149.1 boundary scan, IEEE 1500 embedded core test, and memory built-in self-test concepts.
• Experience with multi-clock and multi-power-domain designs.
• Familiarity with static timing analysis, clock-domain crossing analysis, static power analysis, and physical design closure.
• Experience adapting standard DFT tools or methods to meet the performance requirements of complex, high-frequency designs.
• Demonstrated success collaborating across design, physical design, product engineering, and geographically distributed teams.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.