Senior Silicon Verification Engineer: DFT & IP Tests

Advanced Micro Devices (S) Pte Ltd; Singapore; On-site; SGD 90,000 - 150,000; Full time

Job summary

Advanced Micro Devices (S) Pte Ltd in Singapore is seeking an adaptive, self-motivated design verification engineer to join our growing team. You will drive and improve capabilities to deliver high-quality, industry-leading technologies and collaborate across global sites.

The role focuses on scan test pattern generation for SERDES IPs and SOCs, ATPG pattern analysis, and working with product test teams and physical design engineers to ensure robust design closure.

Qualifications

• Bachelor's or Master's degree in computer engineering or electrical engineering.
• Experience with design-for-test methodologies, especially scan test and ATPG.
• Familiarity with Tessent flows and industry-standard ATPG tools.

Responsibilities

• Own generation, validation, and delivery of scan test patterns for SERDES IPs and SOCs.
• Partner with product test teams during test bring-up and troubleshoot pattern, model, and netlist issues.
• Improve scan architecture, coverage, and test models to enhance product quality.
• Perform ATPG pattern and gate-level netlist analysis to resolve testability issues.
• Collaborate with physical design engineers to support design closure through timing and power analysis.
• Address DFT requirements for high-frequency PHY IP designs while minimizing performance impact.
• Coordinate with global teams to resolve complex interactions between IP and SoC environments.
• Develop and implement improvements to simplify design complexity and strengthen engineering quality.

Skills

Communication skills

Team player

Analytical skills

Problem-solving

Education

Bachelor's or Master's in Computer/Electrical Engineering

Tools

Tessent

ATPG tools

Scan test equipment

Job description

Advanced Micro Devices (S) Pte Ltd in Singapore is seeking an adaptive, self-motivated design verification engineer to join our growing team. You will drive and improve capabilities to deliver high-quality, industry-leading technologies and collaborate across global sites.

The role focuses on scan test pattern generation for SERDES IPs and SOCs, ATPG pattern analysis, and working with product test teams and physical design engineers to ensure robust design closure.