Senior Silicon Design & Verification Engineer

AMD; Singapore; Hybrid; SGD 90,000 - 170,000; Full time

Job summary

AMD is seeking an adaptive design verification engineer to join a global team delivering high-quality, industry-leading technology. You will own the generation and validation of scan test patterns for next-generation SERDES IPs and SOCs, partnering with product test teams to troubleshoot pattern issues and improve coverage.

You’ll work with physical design to support timing, clock-domain, and power analyses while addressing high-frequency DFT requirements.

Qualifications

• Experience with design-for-test methodologies, scan test, and ATPG flow.
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Responsibilities

• Own generation, validation and delivery of scan test patterns for SERDES IPs and SOCs.
• Partner with test teams during bring-up and troubleshoot pattern issues.
• Improve scan architecture, coverage, and test models.
• Perform ATPG pattern and gate-level netlist analysis to resolve issues.
• Collaborate with physical design to support design closure and timing.
• Address DFT requirements for high-frequency Phy IP designs.
• Resolve complex interactions across global teams.
• Develop improvements to simplify design complexity and strengthen engineering quality.

Skills

Scan Test

ATPG

Tessent

Pattern Generation

Multi-clock Domain

Education

Bachelors or Masters degree in computer engineering/Electrical Engineering

Tools

IEEE 1149.1

IEEE 1500

Tessent flows

ATPG debugging

Job description

AMD is seeking an adaptive design verification engineer to join a global team delivering high-quality, industry-leading technology. You will own the generation and validation of scan test patterns for next-generation SERDES IPs and SOCs, partnering with product test teams to troubleshoot pattern issues and improve coverage.

You’ll work with physical design to support timing, clock-domain, and power analyses while addressing high-frequency DFT requirements.