Senior RTL Synthesis Architect & Methodology Lead

black sesame technologies (singapore) pte ltd; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Black Sesame Technologies (Singapore) Pte Ltd is seeking an experienced Synthesis Methodology Engineer to own and drive RTL synthesis methodologies across AI SoC projects. You will develop, maintain, and optimize synthesis flows, evaluate new EDA tools, and enable efficient implementation across multiple technology nodes.

You will collaborate with Design, Backend, CAD, and EDA vendors to improve design productivity and quality, lead sign-off verification with PrimeTime, Formality, VC SpyGlass,

Qualifications

• BS/MS in Electrical or Computer Engineering or related field.
• At least 5 years of ASIC/SoC RTL synthesis or synthesis methodology development.
• Hands-on with Synopsys Design Compiler and RTL synthesis
• Familiar with sign-off tools such as PrimeTime, Formality, VC SpyGlass, and VCLP.
• Experience with timing optimization, synthesis constraints, and ASIC implementation flow.
• Proficiency in Tcl, Shell, or Python for automation and flow development.
• Experience evaluating or deploying Fusion Compiler or Cadence Genus is highly preferred.
• Strong analytical, debugging, and problem-solving skills.
• Excellent communication across cross-functional teams.

Responsibilities

• Develop, maintain, and optimize RTL synthesis flows around ASIC/AI SoC projects.
• Design and improve synthesis methodologies, automation, and reusable workflows across multiple nodes.
• Perform RTL synthesis for AI/NPU blocks ensuring quality and timing convergence.
• Develop and maintain sign-off methodologies using PrimeTime, Formality, VC SpyGlass, and VCLP.
• Support technology node migration and flow enhancements.
• Evaluate, validate, and deploy new EDA tools and methodologies such as Fusion Compiler and Genus.
• Collaborate with RTL designers, Backend, CAD, and EDA vendors to resolve issues.

Skills

RTL synthesis

Automation scripting (Tcl/Python/Shell

Cross-functional collaboration

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Synopsys Design Compiler

Fusion Compiler

Cadence Genus

PrimeTime

Formality

VC SpyGlass

VCLP

Job description

Black Sesame Technologies (Singapore) Pte Ltd is seeking an experienced Synthesis Methodology Engineer to own and drive RTL synthesis methodologies across AI SoC projects. You will develop, maintain, and optimize synthesis flows, evaluate new EDA tools, and enable efficient implementation across multiple technology nodes.

You will collaborate with Design, Backend, CAD, and EDA vendors to improve design productivity and quality, lead sign-off verification with PrimeTime, Formality, VC SpyGlass,