Senior Physical Design Engineer: Chip RTL-to-GDS Lead

BLACK SESAME TECHNOLOGIES (SINGAPORE) PTE. LTD.; Singapore; On-site; SGD 120,000 - 170,000; Full time

Job summary

BLACK SESAME TECHNOLOGIES (SINGAPORE) PTE. LTD. seeks a Senior Physical Design Engineer to drive RTL-to-GDS implementation for complex semiconductor chips in Singapore.

You will lead block-level timing closure, UPF-based power management, and signoff tasks, collaborating with a design team and using industry-standard tools. Preferred candidates have 3+ years in physical design, experience with 7nm/6nm/5nm nodes, and automotive chip design exposure, along with scripting skills in Tcl/Perl/Python

Qualifications

• Bachelor’s degree in Electrical/Computer Engineering or related field.
• Minimum 3 years hands-on physical design experience on complex chips.
• Experience with 7nm, 6nm or 5nm nodes.
• Proficiency in UPF and low power design.
• Experience with block-level APR, STA, PI, PV, FM, and VCLP.
• Proficient with Synopsys and Cadence ARP tools.
• Familiarity with Tcl, Perl, or Python scripting.
• Knowledge of automotive chip physical design standards.

Responsibilities

• Manage RTL to GDS physical design for complex semiconductor chips.
• Achieve block-level timing closure by constraint optimization and timing analysis.
• Conduct formal checks for functional and timing compliance.
• Perform low power checks and analyze power consumption.
• Develop and implement UPF-based power management.
• Conduct block-level APR, STA, PI, PV, FM, and VCLP signoff.
• Utilize Synopsys and Cadence ARP tools for physical design.
• Develop Tcl/Perl/Python scripts to automate design tasks.
• Apply automotive design expertise to meet automotive standards.

Skills

RTL to GDS

Timing closure

UPF

Scripting (Tcl/Python)

Synopsys Cadence ARP

Automotive standards

Low power design

Education

Bachelor’s degree in EE/CE

Tools

Synopsys

Cadence ARP

Job description

BLACK SESAME TECHNOLOGIES (SINGAPORE) PTE. LTD. seeks a Senior Physical Design Engineer to drive RTL-to-GDS implementation for complex semiconductor chips in Singapore.

You will lead block-level timing closure, UPF-based power management, and signoff tasks, collaborating with a design team and using industry-standard tools. Preferred candidates have 3+ years in physical design, experience with 7nm/6nm/5nm nodes, and automotive chip design exposure, along with scripting skills in Tcl/Perl/Python