Lead RTL/SoC Design Engineer for AI ASICs

TetraMem - Accelerate The World; Singapore; On-site; SGD 80,000 - 180,000; Full time

Job summary

TetraMem - Accelerate The World in Singapore seeks a seasoned RTL design engineer to lead RTL design, simulation, and verification for ASIC/SoC products, ensuring robust and efficient designs.

You will collaborate with backend teams, validate IP blocks, perform PPA analysis, mentor junior engineers, and contribute to design reviews, staying current with RTL methodologies to improve product quality and delivery.

Qualifications

• MS with 5+ years of experience in RTL/SoC/digital design
• Proficiency with Verilog and SystemVerilog
• Experience with industry tools (VCS/Verdi) and pre/post-layout simulation
• Familiarity with AMBA/APB/AXI and RISC/Arm architectures

Responsibilities

• Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products.
• Integrate and validate IP blocks within the larger system for seamless functionality.
• Conduct PPA analysis to optimize design trade-offs.
• Collaborate with backend team during RTL coding, implementation, and synthesis for successful tapeout.

Skills

RTL design

Team leadership

Mentorship

Education

MS in Electrical Engineering

PhD in Electrical Engineering (optional)

Tools

Verilog

SystemVerilog

VCS

Verdi

Pre-layout simulation

Post-layout simulation

AMBA APB/AXI

RISC/Arm

UVM

Place-and-route

STA/EM/Power

Job description

TetraMem - Accelerate The World in Singapore seeks a seasoned RTL design engineer to lead RTL design, simulation, and verification for ASIC/SoC products, ensuring robust and efficient designs.

You will collaborate with backend teams, validate IP blocks, perform PPA analysis, mentor junior engineers, and contribute to design reviews, staying current with RTL methodologies to improve product quality and delivery.