Senior Design Engineer: SoC RTL & Block Integration

Silicon Laboratories International Pte Ltd; Singapore; On-site; SGD 90,000 - 140,000; Full time

Job summary

Silicon Labs is seeking a design engineer to advance block architecture and RTL coding for SoC integration in Singapore. You will collaborate with cross-functional teams to define requirements, partition designs, and implement robust digital blocks and IP within the SoC infrastructure.

You will verify blocks and the overall SoC using directed, random, and assertion-based methods, and contribute to embedded firmware for validation and documentation deliverables.

Qualifications

• Detailed block architecture/design of digital circuits.
• Deep understanding of block requirements, system needs and interfaces.
• Develop block specifications with cross-functional teams.
• Determine design approaches and partitioning for blocks.
• Implement design via RTL coding following quality guidelines.
• Integrate digital blocks/IP into SoC infrastructure.
• Develop SoC infrastructure such as bus matrix, memory interfaces, clocking, power and reset management.
• Integrate mixed signal and RF IP.
• Perform block and SoC verification using directed, random and assertion-based methods.
• Develop embedded firmware to verify SoC integration and validation.
• Create and participate in design/architecture/verification reviews.
• Produce customer-facing reference manuals and datasheets.

Responsibilities

• Block architecture/design of digital circuits within the SoC.
• Work with cross-functional teams to develop requirements and specifications.
• Partition design approaches and implement RTL coding adhering to guidelines.
• Integrate digital blocks/IP into SoC infrastructure and RF/mixed-signal IP.
• Verify blocks and SoC using diverse verification methods and cosimulation.
• Develop embedded firmware to assist SoC validation and integration.

Skills

Block architecture design

Block requirements

Block specification

Design approach

RTL coding

SoC integration

IP integration

SoC infrastructure design

RF IP integration

Block verification

Verification methods

SoC verification

Mixed-signal verification

Embedded firmware

Documentation

Reviews

Documentation deliverables

Job description

Silicon Labs is seeking a design engineer to advance block architecture and RTL coding for SoC integration in Singapore. You will collaborate with cross-functional teams to define requirements, partition designs, and implement robust digital blocks and IP within the SoC infrastructure.

You will verify blocks and the overall SoC using directed, random, and assertion-based methods, and contribute to embedded firmware for validation and documentation deliverables.