Synthesis & STA Engineer - Singapore (Chip Signoff)

ByteDance; Singapore; On-site; SGD 110,000 - 160,000; Full time

Job summary

ByteDance seeks an experienced IC design engineer to join the Silicon Platform Team, the core R&D middleware group for chip development. The role covers end-to-end design flow from logic synthesis to tape-out, collaborating closely with front-end and back-end teams.

You will focus on SDC timing signoff, low-power techniques, and formal verification, while driving clean timing closure across multi-clock domains and power integrity considerations.

Qualifications

• Bachelor’s or Master’s degree in electrical engineering, computer engineering, or a related field.
• 3+ years of IC design experience focusing on SDC, synthesis, timing signoff, low-power implementation, and power optimization.
• Proficiency in Verilog/SystemVerilog, RTL-to-GDSII flow, and EDA tools (Fusion Compiler, Genus/Innovus+, PrimeTime/Tempus, Formality, Conformal LP).

Responsibilities

• Perform logic synthesis and design optimization for architectures and RTLs.
• Timing constraints (SDC) preparation and tuning, and conduct hierarchical/full-chip STA signoff and timing closure.
• Implement low-power design techniques and constraints (UPF, clock gating, power gating, dynamic voltage scaling).
• Formal verification & equivalence checking using formal verification tools (Conformal, Formality).
• Work with front-end engineers for architectural exploration and planning.
• Work with backend engineers on floorplanning, place & route (P&R), congestion analysis, and timing bottlenecks.

Skills

Timing analysis

Multi-clock domain handling

DFT awareness

Education

Bachelor's or Master's degree in Electrical/Computer Engineering or related field

Tools

Fusion Compiler

Genus

Innovus

PrimeTime/Tempus

Formality

Conformal LP

Job description

ByteDance seeks an experienced IC design engineer to join the Silicon Platform Team, the core R&D middleware group for chip development. The role covers end-to-end design flow from logic synthesis to tape-out, collaborating closely with front-end and back-end teams.

You will focus on SDC timing signoff, low-power techniques, and formal verification, while driving clean timing closure across multi-clock domains and power integrity considerations.