ASIC Design Engineer — Vision & ISP for Autonomous Driving

Black Sesame Technologies (Singapore) Pte Ltd; Singapore; On-site; SGD 90,000 - 140,000; Full time

Job summary

Black Sesame Technologies (Singapore) Pte Ltd is hiring to assist in designing micro-architecture and RTL for ISP and CV algorithms. You will support power, performance, and area analysis while collaborating with cross-functional teams to verify and validate ASIC designs.

The role involves RTL development in Verilog/SystemVerilog, use of Catapult HLS, and FPGA-related emulation and debugging to facilitate hardware verification and prototype testing. Strong background in ASIC/ISP is required.

Qualifications

• Master’s degree or higher in Electrical, Electronics, or Computer Engineering.
• Experience or project work related to ASIC design or image signal processing.
• Knowledge of C/C++ programming for algorithm implementation and testing.
• Familiarity with ASIC design processes and frontend design methodologies.
• Understanding of image, vision, or video data processing and algorithm acceleration techniques.
• Experience with scripting languages such as Python, Perl, or Tcl to automate tasks and support design workflows.
• Strong teamwork and communication skills to collaborate effectively in cross-functional teams.
• Analytical mindset with a willingness to learn and adapt in a dynamic engineering environment.

Responsibilities

• Design micro-architecture components for image signal processing (ISP) and computer vision (CV) algorithms to support intelligent vehicle solutions
• Develop RTL code using Verilog/SystemVerilog and high-level synthesis (HLS) tools such as Catapult to implement ASIC designs
• Analyze power, performance, and area metrics to optimize design efficiency and meet project requirements
• Collaborate with architects and design verification engineers to ensure thorough verification and successful signoff of designs
• Perform FPGA-related tasks including emulation, validation, and debugging to support hardware verification and prototype testing

Skills

Teamwork

Communication

Analytical mindset

Adaptability

Education

Master’s degree in Electrical/Electronics/Computer Engineering

Tools

Verilog/SystemVerilog

Catapult (HLS)

Python

Perl

Tcl

C/C++

Job description

Black Sesame Technologies (Singapore) Pte Ltd is hiring to assist in designing micro-architecture and RTL for ISP and CV algorithms. You will support power, performance, and area analysis while collaborating with cross-functional teams to verify and validate ASIC designs.

The role involves RTL development in Verilog/SystemVerilog, use of Catapult HLS, and FPGA-related emulation and debugging to facilitate hardware verification and prototype testing. Strong background in ASIC/ISP is required.