SoC Front-End Engineer (Junior–Principal) | RTL & Architecture

manpower staffing services (singapore) pte ltd; Singapore; On-site; SGD 70,000 - 110,000; Full time

Job summary

NSING, part of Nations Technologies Group, is hiring an RTL Design Engineer in Singapore. You will develop synthesizable RTL in Verilog/SystemVerilog, design I2C/XSPI blocks and DMA controllers, and contribute to architecture discussions and PPA trade-offs.

You will build self-test environments, collaborate with verification and backend teams, and ensure design quality through linting and timing closure activities. A strong foundation in digital IC design is essential.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 3–5 years of experience in digital IC design.
• Proficiency in Verilog/SystemVerilog RTL design.
• Experience with simulation and debugging tools.
• Understanding of ASIC/SoC design flow.
• Strong knowledge of digital design fundamentals (FSM, pipelining, clocking, reset strategies).

Responsibilities

• Develop and implement synthesizable RTL code in Verilog/SystemVerilog.
• Design digital blocks such as I2C, XSPI, datapaths, DMA controllers and high-performance interfaces.
• Participate in defining micro-architecture and design specifications; evaluate PPA trade-offs.
• Build self-test environments and collaborate on test plans with verification engineers.
• Integrate IP blocks into the SoC and coordinate with architecture, RTL2GLN, and backend teams.
• Run synthesis and linting, ensure RTL quality meets guidelines and spyglass checks.
• Prepare design documentation including micro-architecture specs, block diagrams, and reports.

Skills

Verilog/SystemVerilog RTL design

Digital IC design fundamentals

Debugging skills

Cross-functional teamwork

Documentation & communication

Education

Bachelor’s or Master’s degree in Electrical/Computer Engineering or related field

Tools

Synopsys Cadence Siemens EDA tools

Job description

NSING, part of Nations Technologies Group, is hiring an RTL Design Engineer in Singapore. You will develop synthesizable RTL in Verilog/SystemVerilog, design I2C/XSPI blocks and DMA controllers, and contribute to architecture discussions and PPA trade-offs.

You will build self-test environments, collaborate with verification and backend teams, and ensure design quality through linting and timing closure activities. A strong foundation in digital IC design is essential.