Senior Research Fellow: Thermo-Mechanical Packaging&3D IC

National University of Singapore; Singapore; On-site; SGD 120,000 - 190,000; Full time

Job summary

The National University of Singapore's ECE Department seeks a Senior Research Fellow to lead thermo-mechanical and thermal simulation research for next-generation semiconductor packaging, including 2.5D/3D and chiplet integration.

The position emphasizes predictive modeling for reliability, high-power AI/HPC applications, and collaboration with academia, industry partners, and government labs. A Ph.D. in a relevant field and 5+ years of related experience are preferred.

Qualifications

• Ph.D. in Electrical, Electronics, Mechanical, Chemical Engineering, Computational Engineering, Applied Physics or equivalent.
• 5+ years of industrial R&D or advanced research in semiconductor packaging, thermal engineering, reliability, or related fields.
• Experience in thermo-mechanical and thermal simulation of advanced electronic packages; publications in related areas is a plus.

Responsibilities

• Develop and execute FEA/multiphysics models to evaluate thermal and mechanical behavior of advanced semiconductor packages.
• Analyze package/system thermal performance, including heat dissipation and cooling strategies.
• Model stresses from CTE mismatch, warpage, and assembly processes.
• Investigate deformation mechanisms in die stacking, TSV integration, and 2.5D/3D packaging.
• Lead a module team and drive innovation for next-generation packaging technologies.

Skills

Thermo-mechanical modeling

Finite element analysis

Heat transfer

Reliability physics

Multiphysics simulation

Education

Ph.D. in Electrical/ Electronics/ Mechanical/ Chemical Engineering/ Computational Engineering/ Applied Physics/ Materials Science

Tools

ANSYS Mechanical

ANSYS Icepak

COMSOL Multiphysics

Abaqus

Job description

The National University of Singapore's ECE Department seeks a Senior Research Fellow to lead thermo-mechanical and thermal simulation research for next-generation semiconductor packaging, including 2.5D/3D and chiplet integration.

The position emphasizes predictive modeling for reliability, high-power AI/HPC applications, and collaboration with academia, industry partners, and government labs. A Ph.D. in a relevant field and 5+ years of related experience are preferred.