Senior ASIC Design Engineer

Espressif Systems; Singapore; On-site; SGD 120,000 - 160,000; Full time

Job summary

Espressif Systems in Singapore is seeking a Senior ASIC Design Engineer to contribute to next-generation AI chips. You will work on micro-architecture, RTL, and IP integration while collaborating with verification and software teams to ensure high-quality digital IC solutions.

You will analyze performance, power, and area, participate in low-power design, and support driver development and technical documentation. The role requires strong Verilog HDL skills and experience with ASIC flows.

Qualifications

• Bachelor’s degree or higher in Electrical Engineering (or equivalent).
• 3+ years of relevant experience in digital IC/ASIC design.
• Strong understanding of digital circuit fundamentals and Verilog HDL.
• Familiarity with ASIC design flow and EDA tools (Synopsys, Cadence).
• Good understanding of CPU and Cache architectures, ISA, and compiler principles.
• Knowledge of bus systems, DMA, and peripheral interface design.
• Awareness of low-power design methodologies.

Responsibilities

• Micro-architecture & RTL development for AI compute subsystems.
• Analyze PPA to deliver high-performance compute within budget.
• RTL design of SoC modules and IP core integration.
• Support chip-level system design tasks: clock/reset, low-power, bus architecture.
• Collaborate with verification and testing teams for validation.
• Assist front-end engineers in netlist delivery and timing issue resolution.
• Provide support for driver development, debugging, and documentation.

Skills

Verilog HDL

Digital IC/ASIC design

EDA tools (Synopsys Cadence)

CPU & Cache architectures

ISA & compiler principles

Bus systems & interfaces

Low-power design methodologies

AMBA/AXI/AHB/APB

Timing analysis

Education

Bachelor’s degree in Electrical Engineering

Tools

Synopsys

Cadence

Job description

We are looking for a talented Senior ASIC Design Engineer to join our growing team in Singapore. In this role, you will be involved to develop the next-generation AI chips based on a revolutionary architecture. You will work closely with verification, front-end, and software teams to deliver high-quality digital IC solutions.

Key Responsibilities:

• Micro-architecture & RTL development for AI compute subsystems.
• Analyze performance, power, and area (PPA) to deliver high-performance compute within strict cost and energy budgets.
• Contribute to RTL design of SoC modules and assist in IP core integration.
• Support chip-level system design tasks, including clock/reset architecture, low-power design techniques, and bus architecture.
• Collaborate with verification and testing teams to perform module-level and system-level validation.
• Assist front-end engineers in netlist delivery and help resolve timing issues.
• Provide support for driver development, debugging, and technical documentation.

Requirements:

• Bachelor’s degree or higher in Electrical Engineering (or equivalent).
• 3 years or above of relevant experience in digital IC/ASIC design.
• Strong understanding of digital circuit fundamentals and proficiency in Verilog HDL.
• Familiarity with ASIC design flow and EDA tools (e.g., Synopsys, Cadence).
• Good understanding of CPU and Cache architectures, instruction set architectures (ISA), and compiler principles.
• Knowledge of bus systems, DMA, and peripheral interface design.
• Awareness of low-power design methodologies.

Preferred Qualifications:

• Familiarity with standard bus protocols (e.g., AMBA, AXI, AHB, APB).
• Exposure to synthesis, timing analysis, or DFT concepts.
• Good problem-solving skills and eagerness to learn in a collaborative environment.
• Strong communication skills and ability to document technical work clearly.