Senior Subsystem Physical Design Engineer

ByteDance; Singapore; On-site; SGD 180,000 - 240,000; Full time

Job summary

ByteDance is seeking a senior physical design engineer in Singapore to own complex digital subsystem implementation from netlist to tapeout. You will drive floorplanning, partitioning, and QoR while coordinating PV/PI signoff across multiple blocks in a fast-paced R&D environment.

The role requires 5+ years in physical design, hands-on PD tool experience (ICC2, Innovus), and familiarity with SoC-level partitioning. Bachelor's degree in EE/CE is required. Regular on-site work in Singapore.

Qualifications

• BS degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
• 5+ years of experience in physical design / physical implementation.
• Experience owning complex digital subsystems from netlist to tapeout.
• Hands-on experience with industry-standard PD tools (e.g., Synopsys ICC2, Cadence Innovus).
• Experience with floorplanning, partitioning, and cross-block timing closure.

Responsibilities

• Own the physical implementation of a complex digital subsystem from netlist handoff through final GDS/tapeout.
• Drive the physical implementation strategy for the subsystem, including SoC-level partition cooperation and subsystem partitioning.
• Define and execute floorplanning and pin assignment.
• Drive PV/PI signoff at the subsystem level.
• Coordinate implementation activities across multiple blocks and ensure consistent methodology and QoR.

Skills

Physical design

Floorplanning

Partitioning

Timing closure

PD tools

Subsystem ownership

Education

BS in Electrical/Computer Engineering

Tools

Synopsys ICC2

Cadence Innovus

Job description

ByteDance is seeking a senior physical design engineer in Singapore to own complex digital subsystem implementation from netlist to tapeout. You will drive floorplanning, partitioning, and QoR while coordinating PV/PI signoff across multiple blocks in a fast-paced R&D environment.

The role requires 5+ years in physical design, hands-on PD tool experience (ICC2, Innovus), and familiarity with SoC-level partitioning. Bachelor's degree in EE/CE is required. Regular on-site work in Singapore.