Senior Physical Design Engineer – PV & Tapeout Focus

ByteDance; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

ByteDance's Silicon Platform Team is seeking a Senior PV Engineer to own PV signoff for advanced-node ASIC/SoC designs. You will lead PV methodology, collaborate with Foundry/EDA vendors, and drive early PDK validation and signoff closure.

You should have 5+ years in physical verification, hands-on PV tool experience, and a strong ability to troubleshoot PV issues across teams. Regular Singapore-based role with cross-functional exposure.

Qualifications

• BS degree in Electrical or Computer Engineering or equivalent practical experience.
• 5+ years of physical verification experience for ASIC/SoC designs.
• Hands-on experience with PV tools and PV signoff flow.

Responsibilities

• Own and drive PV signoff for advanced-node ASIC/SoC designs, including DRC/LVS/ERC checks.
• Manage the PV flow from PDK enablement through tapeout and signoff closure.
• Collaborate with Foundry and EDA vendors on rule-deck bring-up and issue resolution.
• Perform in-depth PV result analysis and regression across PV tool versions.
• Interface between the company and Foundry/PDK teams, tracking issues and validating fixes.

Skills

PV expertise

Team collaboration

Communication skills

Education

BS in Electrical Engineering or equivalent

Tools

Mentor Calibre

Synopsys IC Validator

Job description

ByteDance's Silicon Platform Team is seeking a Senior PV Engineer to own PV signoff for advanced-node ASIC/SoC designs. You will lead PV methodology, collaborate with Foundry/EDA vendors, and drive early PDK validation and signoff closure.

You should have 5+ years in physical verification, hands-on PV tool experience, and a strong ability to troubleshoot PV issues across teams. Regular Singapore-based role with cross-functional exposure.