Senior Layout Engineer

Ace Recruiters; Singapore; On-site; SGD 60,000 - 90,000; Full time

Job summary

Ace Recruiters seeks a permanent layout engineer to realize layout designs from schematics and drive placement, routing, and verification for advanced chip projects.

You will perform DRC/LVS checks, optimize power and signal integrity, and participate in post-layout activities while mentoring junior engineers.

Qualifications

• Diploma or Bachelor's in Electrical/CS/Electronics engineering or equivalent.
• Understanding of AMS layout fundamentals/EMIR/RC delay/latch-up/decoupling caps.
• Experience with technology nodes below 16nm.
• Experience in high-speed or RF layout.
• Experience with TX/RX/PLL/ADC/DAC is a plus.
• Cadence and pcell development tooling; automation to boost productivity.
• Hands-on layout engineering experience.
• Familiar with CAD tools and finfet technology.
• Experience with analog/digital chip-top integration.
• Understanding of process tech and circuit design.
• Knowledge of analog layout physical verification CAD setup.

Responsibilities

• Realize layout design from schematic presentation.
• Layout implementation: floor planning, device placement, routing, and integrity.
• Perform DRC/LVS/ERC/ANT/ESD/PERC/LVL checks and verifications.
• Prepare materials and review layout quality and methodology.
• Participate in post-layout adjustments and IP activities.
• Mentor junior layout engineers and share best practices.
• Contribute to layout methodologies and improvements.

Skills

Layout engineering

Mentoring

Automation

Physical verification

Education

Electrical/Computer/Electronics Eng degree

Tools

Cadence (pcell development)

Perl

Python

Tcl

Job description

This is a permanent position attached to aCompanywhich develops chips for Data Processing, IP Licensing, Network, Bus, Chiplet Interconnect as well as Chip Customization for different customers

Location: North East

Job Scope

• Realize layout design from schematic presentation.
• Layout design implementation includes the following functions:
• Floor planning and device placement
• Power and Signal routings and Integrity optimization
• DRC/LVS/ERC/ANT/ESD/PERC/LVL and necessary Physical Verification
• Passing DRC rules and ensuring LVS
• Preparing material and reviewing of layout
• Checklist/Methodology to ensure quality of layout
• Layout methodology and enhancement
• Participate in post layout adjustments and block/IP activities
• Mentoring of junior layout engineers
• Participate in development of layout best practices and methodology

Requirements

• Diploma or Bachelor’s in Electrical/Computer/Electronics Engineering or equivalent.
• Good understanding of AMS layout fundamentals/EMIR/RC delay/Decoupling Caps/Latch-up
• Experience working on technology node below 16nm
• Experience working on high-speed or RF layout.
• Experience in TX/RX/PLL/ADC/DAC/etc. is a plus.
• Experience working with Cadence skills or equivalent tools for pcell development (perl/python/tcl) and automation to increase layout productivity.
• Hands-on working experience in layout engineering.
• Experience working with leading industry CAD tools, methodology and finfet technology.
• Experience with analog/digital on top (chip-top) integration is a plus point.
• Understanding of process technology and circuit design.
• Understanding of analog layout physical verification CAD setup.

Work Hours

Monday to Friday 9am to 6pm, 5 day week