IC Layout Engineer

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; Singapore; On-site; SGD 90,000 - 140,000; Full time

Job summary

Broadcom Inc. in Singapore is seeking a skilled IC Layout Engineer to execute high-quality layouts for Standard Cells, I/O pads, and Mixed-Signal IP in advanced nodes.

You will manage layout schedules from transistor level to floorplanning, collaborate across sites, and use Cadence Virtuoso with Calibre for DRC/LVS/ERC analysis; knowledge of 5nm+ nodes and SKILL scripting is a plus. This position offers a challenging role in a global leader in semiconductors.

Qualifications

• Bachelor’s degree in Electronic Engineering.
• 3 to 4+ years of hands-on IC layout experience.

Responsibilities

• Apply design guidelines and advanced rules to deliver high-performance layouts for Standard Cells, I/O pads and Mixed-Signal IP.
• Manage layout schedules from transistor level to cell- and block-level floorplanning.
• Adopt new layout methodologies to improve quality and efficiency.
• Communicate with engineers across sites to ensure alignment.
• Use Cadence Virtuoso to create and verify layouts.
• Perform DRC, LVS, ERC, Antenna, and EM/IR checks with Calibre.
• Apply ESD and latch-up knowledge for reliable I/O design.
• Understand deep sub-micron/nodes (5nm, 3nm, 2nm, 1.4nm) to optimize layout.
• Use Shell/Python/Tcl or Cadence SKILL to automate tasks.
• Work independently yet collaborate as a team player.

Skills

IC layout

Cadence Virtuoso

Scripting (Shell/Python/Tcl/Cadence SK

Education

Bachelor’s degree in Electronic Engineering

Tools

Cadence Virtuoso

Calibre

Shell scripting

Python

Tcl

Cadence SKILL

Job description

Company Overview

Broadcom Inc. is a global technology leader designing and supplying semiconductor and infrastructure software solutions. Its products serve critical markets including data center, networking, software, broadband, wireless, storage, and industrial sectors. For more information, visit www.broadcom.com.

Job Summary

Responsible for executing high-quality layouts across Standard Cells, I/O pads, and Mixed-Signal IP in advanced processes within project schedules.

Responsibilities

• Apply design guidelines and advanced process rules to deliver high-performance, robust layouts for Standard Cells, I/O pads, and Mixed-Signal IP
• Manage and execute layout schedules independently from transistor level to cell- and block-level floorplanning
• Adapt to emerging layout methodologies and incorporate new ideas to improve layout quality and efficiency
• Communicate effectively with engineers across multiple sites to ensure alignment and collaboration
• Utilize Cadence Virtuoso layout tool to create and verify layouts
• Perform physical verification using Calibre tools for DRC, LVS, ERC, Antenna, and EM/IR analysis
• Apply knowledge of ESD and Latch-up principles to ensure reliable I/O design
• Demonstrate understanding of deep sub-micron and advanced nodes (e.g., 5nm, 3nm, 2nm, 1.4nm) to optimize layout performance
• Use scripting skills in Shell, Python, Tcl, or Cadence SKILL programming to automate layout tasks and improve productivity
• Work independently with self-motivation while contributing as a collaborative team player

Required competencies and certifications

• Bachelor’s degree in Electronic Engineering
• 3 to 4+ years of hands-on IC layout experience

Preferred competencies and qualifications

• Scripting knowledge in Shell, Python, Tcl, or Cadence SKILL programming