Senior Integrated Circuit Designer - Layout

ASTERA LABS SINGAPORE PRIVATE LIMITED; Singapore; On-site; SGD 70,000 - 90,000; Full time

Job summary

A leading technology company located in Singapore is seeking an Integrated Circuit Designer. The ideal candidate will have a bachelor's degree in electrical engineering and at least 2 years of experience in developing layouts for high-speed analog IC designs, particularly in finFET technology. Key responsibilities include designing integrated circuit layouts, managing the manufacturing processes, and developing test programs to ensure product quality. This role provides an exciting opportunity to work on sophisticated advanced node CMOS products.

Qualifications

• At least a bachelor’s degree in electrical engineering.
• 2+ years of experience in high-speed analog IC design.

Responsibilities

• Design and develop integrated circuit layouts.
• Manage manufacturing processes including yield performance.
• Develop test programs to ensure performance specifications.

Skills

Layout extraction

High-speed analog IC designs

EMIR and antenna DRC rules

SKILL scripting

TCL scripting

Education

Bachelor’s degree in electrical engineering

Job description

The company seeks a highly motivated and team-oriented individual to work with both layout and design engineers across multiple time zones

As an Integrated Circuit Designer, you will be part of a key team designing and developing sophisticated advanced node CMOS products.

Key Job Duties:

• The design and development of the layout for integrated circuits according to electronics engineering principles, using software to create design schematics and diagrams. This will include [floor planning, creating layouts of building blocks and integrating layouts for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs in advanced CMOS nodes. Your focus will include minimizing parasitic and skew, matching, EMIR, and antenna rules on top of DRC and LVS]
• The management of manufacturing process of the products, including technology yield and performance of the products.
• The development of test programmes and procedures to ensure the products meet their performance specifications.
• The provision of advice on aspects of semiconductor process technology and maintain and repair semiconductor process equipment.

Basic Qualifications:

• At least a bachelor’s degree in electrical engineering

Required Experience:

• 2+ years of experience in the development of layouts for highspeed analog IC designs in finFET technology.
• Experience with layout extraction tools and to analyzing layout parasitic to achieve high quality layout for highspeed circuits.
• EMIR and antenna DRC rules aware layout practices.
• Experience writing SKILL and TCL scripts is highly recommended