Senior / Analog Layout Engineer

AUREXIS TECH PTE. LTD.; Singapore; On-site; SGD 60,000 - 100,000; Full time

Job summary

AUREXIS TECH PTE. LTD. in Singapore is seeking a skilled layout engineer to design and verify analog, digital, and mixed-signal circuits for advanced semiconductor IPs. You will own major IP block layouts, collaborate with analog designers on floorplanning, and perform physical verifications (DRC/LVS/ERc) to ensure reliability and performance.

The ideal candidate has 3+ years in CMOS layout, strong teamwork, and good communication.

Qualifications

• Degree/Diploma in Electrical/Electronics/Computer Engineering with at least 3 years of relevant experience.
• Knowledge of CMOS circuit theory.
• Solid experience in analog layout design.
• Layout design and verification using Cadence Virtuoso and Mentor Calibre.
• Experience in LVS, DRC, ERC, ANT, ESD, latch-up, EMIR and Reliability.
• Good understanding of signal and clock shielding and isolation techniques.
• Good communication and team player.

Responsibilities

• Design layout for analog, digital and mixed-signal circuits.
• Own layout of major custom IP blocks.
• Work closely with analog designers on floorplanning and layout implementation.
• Physical and electrical verification including DRC, LVS, EM/IR, ERC, PERC latch up and PERC ESD
• Review resource deliverables and ensure quality/milestone completion.
• Plan schedules and drive assigned blocks to meet project timelines.

Skills

CMOS circuit theory

Analog layout design

Layout verification

Signal shielding

Communication skills

Team player

Education

Degree/Diploma in Electrical/Electronics/Computer Engineering

Tools

Cadence Virtuoso

Mentor Calibre

LVS

DRC

ERC

Job description

Main Responsibilities

• Design layout for analog, digital andmixed-signal circuits.


• Own layout of major custom IP blocks.


• Work closely with analog designers on floorplanning and layout implementation.


• Physical and electrical verificationinclude DRC, LVS, EM/IR, ERC, PERC Latch up and PERC ESD


• Review resource deliverables and ensurequality/milestone completion.


• Plan schedules and drive assigned blocks tomeet project timelines.

Main Requirements

• Degree/Diploma in Electrical/ Electronics/ Computer Engineering with minimum 3 years of relevant experiences.


• Must have knowledge of CMOS circuit theory


• Solid experience in analog layout design


• Layout design and verification experience using Cadence Virtuoso and Mentor Calibre


• Experience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability


• Good understanding of signal and clock shielding and isolation techniques


• Good communication skill and team player