[2027 Campus Hire] Full Custom Layout Engineer

MediaTek; Singapore; On-site; SGD 39,000 - 61,000; Full time

Job summary

MediaTek’s Layout team seeks result-driven graduates to contribute to top-quality IC layout for our chips. You will engage in floor-planning, power mesh, and routing while adapting to a fast-paced environment and learning advanced semiconductor processes.

The role emphasizes collaboration with multi-site teams, applying DRC/LVS/ERC checks, and ensuring tape-out readiness. Fresh graduates with problem-solving mindset and scripting skills are encouraged to apply.

Qualifications

• Degree required in Electrical/Electronic Engineering.
• Experience with transistor-level circuits and device layout preferred.
• Familiarity with EDA tools via projects or internships is an advantage.
• Strong analytical and problem-solving abilities with attention to detail.
• Good teamwork and time management.

Responsibilities

• Implement top-quality IC layout meeting designers' specs and milestones.
• Perform physical and reliability verifications (DRC/LVS/ERC) on layouts.
• Collaborate with cross-site teams to optimize power, performance, area, and schedule.
• Contribute to in-house IP/library developments.

Skills

Transistor-level knowledge

Analytical skills

Problem solving

Time management

Scripting (Tcl/Perl)

Education

Bachelor’s degree in Electrical/Electronic Engineering

Tools

Cadence Virtuoso

Synopsys

Calibre

Job description

Job Description

MediaTek’s Layout team is responsible to implement top quality layout of the integrated circuit for our chips. We are looking for result-driven candidates who can thrive under a fast-pace working environment and possess a strong desire to create an impact in the organization. Fresh graduates who are eager to get involved with industry most advanced semiconductor process technology are a perfect fit for our team. Candidates with strong passion in learning, problem solving, and decision-making skills are welcome to apply. Candidates will be able to develop in the following area: - Strong knowledge in floor-planning techniques at different hierarchies, with emphasis on power mesh planning, critical block placement, critical signal routing, matching and top-down integration flow - Proficient in Synopsys/Cadence layout editor and physical verification tools; analytical and skillful in debugging DRC/LVS and all other verifications [What you will do] - Implement top quality layout which meet the specifications set forth by designers and layout leads while meeting the project objectives and fast paced milestones - Diligently perform all physical & reliability verifications (DRC/LVS/ERC/etc.) on the layout designs and ensure the database is fully compliant with all requirements of tape-out flow - Work closely and communicate effectively with multi-functional teams and multi-site to constantly optimize layout for better power, performance, area and schedule - Responsible for in-house IP/library developments

Main Requirements and Qualifications

• [Are you the right talent?]
• - Bachelor’s degree in Electrical/Electronic Engineering Has transistor level knowledge for circuits and device layout structure
• - Exposure to EDA tools such as Cadence Virtuoso, Synopsys or Calibre through academic projects or internships is an advantage.
• - Has a strong analytical and problem-solving skills with attention to details.
• - Has good working ethic, a team player and effective in cross-team communication and time management
• - Proficiency in script programming (e.g. Tcl, Perl or C-shell) is a plus