Senior IC Layout Engineer for SoC Integration

CURIOUS TEK PTE. LTD.; Singapore; On-site; SGD 100,000 - 145,000; Full time

Job summary

CURIOUS TEK PTE. LTD. in Singapore is seeking an experienced IC Layout Engineer to develop digital and analog CMOS layouts and support SoC integration.

You will work on layout tasks across multiple technologies and help optimize layout quality. The role requires a bachelor’s degree in Electrical & Electronic Engineering, at least 5 years of layout design experience, and strong knowledge of EDA tools such as Cadence, Synopsys, and Calibre.

Qualifications

• At least a bachelor’s degree in Electrical & Electronic Engineering or related field with IC design background (analog/digital).
• 5+ years of layout design experience.
• Knowledge of EDA tools (Cadence, Synopsys, Mentor Graphics Calibre).
• Familiar with layout reliability considerations (ESD, latch-up, aging, EMIR).
• Able to troubleshoot DRC/LVS layout verification errors and follow signoff flow.
• Strong communication, independence, and teamwork.

Responsibilities

• Develop digital and analog layout in various technologies (e.g., CMOS).
• Layout analog circuits and IO circuits.
• Analyse and rectify layout verification issues.
• Support the front-end team for System-on-Chip (SoC) integration.

Skills

Layout design

Analog layout

Digital layout

EDA tools

DRC/LVS signoff

SoC integration support

Troubleshooting

Communication

Education

Bachelor's degree in Electrical & Electronic Engineering

Tools

Cadence

Synopsys

Mentor Graphics Calibre

Job description

CURIOUS TEK PTE. LTD. in Singapore is seeking an experienced IC Layout Engineer to develop digital and analog CMOS layouts and support SoC integration.

You will work on layout tasks across multiple technologies and help optimize layout quality. The role requires a bachelor’s degree in Electrical & Electronic Engineering, at least 5 years of layout design experience, and strong knowledge of EDA tools such as Cadence, Synopsys, and Calibre.