Senior Digital Implementation & STA Engineer

FOCALTRANS PTE. LTD.; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

FOCALTRANS PTE. LTD. is seeking a Digital Implementation/ STA Engineer to support ASIC development, covering logic synthesis, formal verification, timing analysis and timing closure.

You will collaborate with frontend and backend teams to ensure robust timing constraints and efficient implementation flows. Ideal candidates have strong Verilog skills, deep knowledge of STA and full-chip timing closure, experience with EDA tools such as Synopsys DC and PrimeTime, and scripting (Tcl/Perl/Python).

Qualifications

• Education: Bachelor’s degree or above in Electronic Information Engineering, Microelectronics, Integrated Circuit Engineering, AI or related field.
• Strong Verilog proficiency and knowledge of logic synthesis flows and full-chip synthesis strategies.
• Solid understanding of STA, timing closure methods and timing ECO implementation.
• Hands-on experience with EDA tools for logic synthesis, formal verification and STA; scripting in Tcl/Perl/Python.
• Familiarity with DFT concepts (BIST, SCAN, JTAG, ATPG) is a plus.
• Self-motivated, proactive, able to work independently with good communication and teamwork.

Responsibilities

• Develop, maintain and ensure quality of logic synthesis, formal verification and STA flows.
• Develop and review module-level timing constraints and full-chip SDC; perform quality checks.
• Execute full-chip STA and timing closure; coordinate timing ECOs with frontend/backend teams.

Skills

ASIC / Digital IC Design

Logic Synthesis

Static Timing Analysis (STA)

Timing Closure

SDC

Timing ECO

Formal Verification

Verilog

Synopsys Design Compiler (DC)

Formality

PrimeTime (PT)

Tcl / Perl / Python

DFT / BIST / SCAN / JTAG / ATPG

Education

Bachelor’s degree in Electronic Information Engineering, Microelectronics, Integrated Circuit Engineering, Artificial Intelligence, or related

Tools

Synopsys Design Compiler (DC)

Formality

PrimeTime (PT)

Tcl

Python

Job description

FOCALTRANS PTE. LTD. is seeking a Digital Implementation/ STA Engineer to support ASIC development, covering logic synthesis, formal verification, timing analysis and timing closure.

You will collaborate with frontend and backend teams to ensure robust timing constraints and efficient implementation flows. Ideal candidates have strong Verilog skills, deep knowledge of STA and full-chip timing closure, experience with EDA tools such as Synopsys DC and PrimeTime, and scripting (Tcl/Perl/Python).