Staff Digital IC Design Engineer

ZERRO POWER SYSTEMS PTE. LTD.; Singapore; On-site; SGD 75,000 - 95,000; Full time

Job summary

A leading technology firm in Singapore is looking for a skilled engineer with expertise in RTL-level digital design and FPGA verification. The ideal candidate should hold a Bachelor/Masters in Electronics/Electrical Engineering and possess 7-10 years of experience. Responsibilities include guiding junior engineers, collaborating with backend teams, and performing digital functional verification. Proficiency in Verilog coding and experience with Cadence tools are strongly preferred, making this an excellent opportunity for a seasoned professional.

Qualifications

• 7-10 years of experience in application/validation.
• Experience in defining and implementing custom digital interfaces.
• Knowledge of working with multiple clock domains.

Responsibilities

• Lead and guide junior engineers.
• Verify digital functions and support backend teams.
• Conduct RTL design for different applications.

Skills

RTL-level digital design

Verilog coding

Digital synthesis

FPGA verification

Mixed Signal IC design

Logic synthesis

Education

Bachelor/Masters in Electronics/Electrical Engineering

Tools

Cadence tools

Job description

Overview

• RTL-level digital design and problem solving
• Function verification and support
• Work closely with backend team on Digital synthesis, place-and-route, Design for Test and Static timing analysis
• Lead and guide junior engineers
• Digital functional verification and FPGA verification

Job Requirements

• Bachelor/Masters in Electronics/Electrical Engineering with Mixed Signal IC design/verification experience.
• At least 7-10 Year(s) of working experience in application/ validation
• Fluent in Verilog coding, design, simulation, and verification domains
• Definition and implementation of custom digital interfaces (I2C, 3-wire, single_wire etc.)
• Definition and implementation of custom finite state machines, register maps, control logic which interface with analog circuits such as drivers and proprietary IPs like OTP or flash memory
• RTL design for synchronous and asynchronous applications, including multiple clock domains
• Basic knowledge of Logic synthesis, place & route, static timing analysis, logic equivalency checking
• Usage of Cadence tools like Incisive Enterprise Simulator, SimVision, Genus, First Encounter, Conformal, Modus, Tempus and Virtuoso will be preferred