ASIC STA Engineer

Black Sesame Technologies (Singapore) Pte Ltd; Singapore; On-site; SGD 45,000 - 69,000; Full time

Job summary

Black Sesame Technologies is seeking fresh graduates to join as ASIC STA Engineers. This entry-level role focuses on timing closure, verification, constraints (SDC), and timing analysis to ensure chip performance and integrity.

You will work closely with front-end and back-end teams to drive PPA targets and learn the ASIC design flow. The position emphasizes learning, collaboration, and proactive problem-solving while contributing to innovative projects in ASIC timing analysis and design

Qualifications

• Master’s degree or higher in Electronics Engineering, Computer Science, or a related field.
• Fundamental knowledge of ASIC timing analysis and synthesis.
• Familiarity with the ASIC development process and design flow.
• Proficiency in programming languages such as Perl, Tcl, Python, or similar.
• Strong communication skills and collaborative, proactive problem-solving attitude.

Responsibilities

• Oversee timing closure at the block level throughout the project lifecycle to ensure design integrity.
• Develop and maintain methodologies for timing verification and closure.
• Collaborate with designers to generate and implement timing constraints (SDC).
• Conduct detailed timing analysis to verify designs meet specifications and performance metrics.
• Assist in constructing and refining workflows to improve efficiency in timing analysis processes.
• Collaborate with front-end and back-end teams to achieve the chip PPA target.

Skills

Perl

Python

Tcl

Education

Master’s degree or higher in Electronics Engineering, Computer Science, or related field

Job description

Black Sesame Technologies is seeking motivated and talented fresh graduates to join our team as ASIC STA Engineers. This entry-level position offers an excellent opportunity for recent graduates to embark on a career in ASIC design and timing analysis. We are looking for individuals who are eager to learn and contribute to our innovative projects.

Responsibilities:

• Timing Closure: Oversee timing closure at the block level throughout the project lifecycle to ensure design integrity.
• Timing Verification: Develop and maintain methodologies and workflows for timing verification and closure, ensuring effective timing management.
• Timing Constraints: Collaborate with designers to generate and implement timing constraints (SDC) critical for design performance.
• Timing Analysis: Conduct detailed timing analysis to verify that designs meet required specifications and performance metrics.
• Flows: Assist in constructing and refining workflows to improve efficiency and effectiveness in timing analysis processes.
• Coordinator Role: Collaborate with front-end and back-end teams to achieve the chip PPA (Power, Performance, Area) target.

Qualification/ Requirements:

• Education: Master’s degree or higher in Electronics Engineering, Computer Science, or a related field.
• Fundamental knowledge of ASIC timing analysis and synthesis.
• Familiarity with the ASIC development process and design flow.
• Proficiency in programming languages such as Perl, Tcl, Python, or similar.
• Strong communication skills, a collaborative team approach, and a proactive attitude towards learning and problem-solving.