Timing & STA Engineer for Full-Chip Digital Impl

FLAMINGO RECRUITMENT PTE. LTD.; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

Flamingo Recruitment Pte. Ltd. in Singapore is seeking an experienced IC Design Verification Engineer to develop, optimize, and verify flows for logic synthesis, formal verification, and STA, ensuring high-quality timing closure.

You will collaborate with front-end teams to define module-level and full-chip SDC constraints and execute full-chip STA to identify and fix timing issues. The role requires strong Verilog and SDC skills, hands-on experience with EDA tools, and proficiency in Tcl, Perl,

Qualifications

• ,

Responsibilities

• Develop, maintain, and optimize flows for logic synthesis, formal verification, and STA, ensuring quality, accuracy, and efficiency.
• Develop and review module-level and full-chip SDC timing constraints with front-end design teams.
• Execute full-chip STA, identify timing issues, and drive timing closure.
• Implement timing ECOs and collaborate with front-end and back-end teams to resolve timing-related issues.

Skills

Verilog

Python

Tcl

Perl

Problem solving

Education

Bachelor's degree or above in Electronics/IC/AI

Tools

EDA tools

Synthesis tools

Formal verification tools

STA tools

SDC

Job description

Flamingo Recruitment Pte. Ltd. in Singapore is seeking an experienced IC Design Verification Engineer to develop, optimize, and verify flows for logic synthesis, formal verification, and STA, ensuring high-quality timing closure.

You will collaborate with front-end teams to define module-level and full-chip SDC constraints and execute full-chip STA to identify and fix timing issues. The role requires strong Verilog and SDC skills, hands-on experience with EDA tools, and proficiency in Tcl, Perl,