Senior IC Logic & Timing Closure Engineer

FOCALTRANS PTE. LTD.; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

FOCALTRANS PTE. LTD. in Singapore seeks an experienced IC design professional to drive logic synthesis, LEC and ECO implementation, and to work with frontend teams to establish timing constraints and achieve timely timing closure.

The role also covers full-chip STA execution and timing sign-off, collaborating with backend teams to ensure robust timing closure across the project. Candidates should hold a Bachelor’s degree or higher in Computer/Electrical/Electronic/Communications Engineering and

Qualifications

• Bachelor’s degree or above in Computer Engineering, Electrical/Electronic Engineering, Communications Engineering or a related discipline.
• 8+ years of relevant industry experience.
• Strong proficiency in SDC and hands-on experience with Design Compiler (DC), Formality and PrimeTime (PT); Tcl scripting.

Responsibilities

• Logic synthesis, LEC and ECO implementation with timing constraints and timing closure.
• Full-chip STA execution and timing sign-off, collaborating with back-end design teams to ensure timing closure.

Job description

FOCALTRANS PTE. LTD. in Singapore seeks an experienced IC design professional to drive logic synthesis, LEC and ECO implementation, and to work with frontend teams to establish timing constraints and achieve timely timing closure.

The role also covers full-chip STA execution and timing sign-off, collaborating with backend teams to ensure robust timing closure across the project. Candidates should hold a Bachelor’s degree or higher in Computer/Electrical/Electronic/Communications Engineering and