STA Engineer

Uni Connect; Singapore; On-site; SGD 75,000 - 95,000; Full time

Job summary

A leading tech company in Singapore seeks an experienced STA Engineer to perform detailed timing analysis on digital designs for networking and audio solutions. The role requires a Bachelor’s or Master’s degree in Electrical Engineering and over 6 years of relevant experience. Candidates should be proficient in STA tools like Synopsys PrimeTime and have strong scripting skills in TCL, Perl, or Python. Ideal candidates will have knowledge of digital design principles and CMOS technology, focusing on high-performance applications.

Qualifications

• 6+ years of experience in STA for digital ICs.
• Experience with timing analysis for designs at 28nm and below.
• Familiarity with low-power design techniques and their impact on timing.

Responsibilities

• Perform detailed STA on digital designs used in networking and audio solutions.
• Identify and resolve timing violations in critical paths.
• Conduct multi-mode, multi-corner analysis to ensure timing closure.

Skills

Strong understanding of digital design principles

Scripting skills (TCL, Perl, Python)

Excellent communication skills

Problem-solving skills

Education

Bachelor’s or Master’s degree in Electrical Engineering

Tools

Synopsys PrimeTime

Cadence Tempus

Job description

Singapore, Singapore | Posted on 12/17/2024

• PerformdetailedSTAon digital designs used in networking and audiosolutions at various stages of the IC design flow (pre-layout,post-layout).
  
• Identify, analyze, andresolve timing violations in critical paths, ensuring low latency and highthroughput for networking and audio processing applications.
  
• Conduct multi-mode,multi-corner (MMMC) analysis to ensure timing closure under differentoperating conditions, including power-saving modes.
  
• Develop, validate, andoptimize timing constraints tailored for high-speed networking interfacesand high-fidelity audio processing circuits.
  
• Define and validateclock definitions, I/O constraints, multi-cycle paths, and false paths,ensuring robust performance in real-world applications.
  
• Work closely with thePhysical Design team to address timing issues, suggest optimizations, andsupport clock distribution for complex networking and audio processingcircuits.
  
• Perform final timinganalysis and sign-off, ensuring that our ICs meet stringent timing, area,and power requirements for networking and audio applications.
  
• Work with post-siliconvalidation teams to correlate timing models with actual siliconmeasurements, ensuring that our networking and audio solutions perform asexpected in the field.
  

Requirements

Requirements:

• Bachelor’s or Master’sdegree in Electrical Engineering, Computer Engineering, or a relatedfield.
  
• 6+ years of experienceinSTAfor digital ICs, preferably in the networking or audiodomain.
  
• Strong understanding ofdigital design principles, timing concepts, and semiconductor physics.
  
• Experience with timinganalysis for designs at 28nm and below, with a focus on high-speed dataand signal processing.
  
• ProficiencyinSTAtools such as Synopsys PrimeTime, Cadence Tempus, orsimilar.
  
• Solid understanding ofCMOS technology, standard cell libraries, and PVT variations, with a focuson high-performance networking and audio applications.
  
• Strong scripting skills(e.g., TCL, Perl, Python) for automation ofSTAprocesses.
  
• Ability to work in acollaborative environment, with excellent communication andproblem-solving skills.
  
• Experience with timinganalysis for high-speed networking interfaces (e.g., Ethernet, Wi-Fi) oraudio processing circuits (e.g., DACs, ADCs).
  
• Familiarity withlow-power design techniques and their impact on timing.