Senior Digital Implementation / STA Engineer

FOCALTRANS PTE. LTD.; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

FOCALTRANS PTE. LTD. is seeking a Digital Implementation/ STA Engineer to support ASIC development, covering logic synthesis, formal verification, timing analysis and timing closure.

You will collaborate with frontend and backend teams to ensure robust timing constraints and efficient implementation flows. Ideal candidates have strong Verilog skills, deep knowledge of STA and full-chip timing closure, experience with EDA tools such as Synopsys DC and PrimeTime, and scripting (Tcl/Perl/Python).

Qualifications

• Education: Bachelor’s degree or above in Electronic Information Engineering, Microelectronics, Integrated Circuit Engineering, AI or related field.
• Strong Verilog proficiency and knowledge of logic synthesis flows and full-chip synthesis strategies.
• Solid understanding of STA, timing closure methods and timing ECO implementation.
• Hands-on experience with EDA tools for logic synthesis, formal verification and STA; scripting in Tcl/Perl/Python.
• Familiarity with DFT concepts (BIST, SCAN, JTAG, ATPG) is a plus.
• Self-motivated, proactive, able to work independently with good communication and teamwork.

Responsibilities

• Develop, maintain and ensure quality of logic synthesis, formal verification and STA flows.
• Develop and review module-level timing constraints and full-chip SDC; perform quality checks.
• Execute full-chip STA and timing closure; coordinate timing ECOs with frontend/backend teams.

Skills

ASIC / Digital IC Design

Logic Synthesis

Static Timing Analysis (STA)

Timing Closure

SDC

Timing ECO

Formal Verification

Verilog

Synopsys Design Compiler (DC)

Formality

PrimeTime (PT)

Tcl / Perl / Python

DFT / BIST / SCAN / JTAG / ATPG

Education

Bachelor’s degree in Electronic Information Engineering, Microelectronics, Integrated Circuit Engineering, Artificial Intelligence, or related

Tools

Synopsys Design Compiler (DC)

Formality

PrimeTime (PT)

Tcl

Python

Job description

About the Role

We are looking for a Digital Implementation / STA Engineer to support ASIC development activities covering logic synthesis, formal verification, timing analysis and timing closure. The successful candidate will work closely with front-end and back-end design teams to ensure robust timing constraints, efficient implementation flows and successful full-chip timing closure.

Key Skills

• ASIC / Digital IC Design
• Logic Synthesis
• Static Timing Analysis (STA)
• Timing Closure
• SDC
• Timing ECO
• Formal Verification
• Verilog
• Synopsys Design Compiler (DC)
• Formality
• PrimeTime (PT)
• Tcl / Perl / Python
• DFT / BIST / SCAN / JTAG / ATPG

Key Responsibilities

1. Logic Synthesis, Formal Verification & STAResponsible for the development, maintenance and quality control of flows related to logic synthesis, formal verification and Static Timing Analysis (STA).Ensure the robustness, accuracy and efficiency of relevant implementation flows.
2. Timing Constraint DevelopmentWork closely with the front-end design team to develop and review module-level timing constraints.Collaborate with the front-end team to develop and perform quality checks on full-chip flattened SDC (Synopsys Design Constraints).
3. Full-Chip Timing Analysis & ClosureExecute full-chip STA and perform timing analysis.Responsible for full-chip timing ECOs and support overall timing closure.Work closely with front-end and back-end design teams to identify and resolve timing-related issues.

Job Requirements

1. Education & BackgroundBachelor’s degree or above in Electronic Information Engineering, Microelectronics, Integrated Circuit Engineering, Artificial Intelligence, or a related discipline.
2. Logic Synthesis & Formal VerificationStrong proficiency in Verilog.Solid understanding of logic synthesis flows, methodologies and full-chip synthesis strategies.Experience in formal verification debugging is preferred.
3. STA & Timing ClosureStrong proficiency in SDC.Good understanding of full-chip Static Timing Analysis (STA) and timing closure methodologies.Experience with timing analysis and timing ECO implementation is preferred.
4. EDA Tools & ScriptingHands-on experience with commonly used EDA tools for logic synthesis, formal verification and static timing analysis.Proficiency in Tcl, Perl and Python scripting.Strong scripting and flow automation capabilities will be an advantage.
5. DFT KnowledgeFamiliarity with Design for Test (DFT) concepts is preferred.Knowledge of common DFT methodologies, including BIST, SCAN, JTAG and ATPG, will be an advantage.
6. Professional CompetenciesSelf-motivated, proactive and capable of working independently.Strong analytical and problem-solving skills.Good communication and teamwork skills.Demonstrates a strong sense of ownership and commitment to delivering high‑quality results.