Senior / DFT Engineer

alpsoft technologies pte. ltd.; Singapore; On-site; SGD 70,000 - 110,000; Full time

Job summary

alpsoft technologies pte. ltd. is seeking a DFT Engineer to develop and optimize testability for digital and mixed-signal IP. You will implement DFT logics, generate ATPG patterns, and support ATE tooling for prototyping and production testing.

Candidates should have a Bachelor’s in Electrical or Computer Engineering, strong problem-solving and communication skills, and familiarity with HDL; experience with Cadence tools is a plus.

Qualifications

• Bachelor degree or equivalent in Electrical or Computer Engineering.
• Familiar with HDL design language.
• Experience with ASIC design and ATE test is a plus.
• Strong problem solving and communication skills.
• Cadence tools experience.

Responsibilities

• DFT implementation of Scan Logic, IJTAG, MBIST Logic.
• Analysis to improve testability of Digital design at Block and chip level.
• Implementation of DFT logics for Digital and Mixed Signal IP.
• Perform ATPG pattern generation including SSA /Transition/ Path Delay and IDDQ pattern.
• Perform ATPG verification and simulation playback.
• Deliver high quality ATE patterns for production ATE testing.
• Provide test pattern support to ATE engineering team for First Proto bring up and failure analysis.

Skills

DFT concepts

HDL familiarity

UNIX/Linux

Scripting (TCL, Perl, cshell)

Problem solving

Teamwork

Communication

Education

Bachelor's degree in Electrical or Computer Engineering

Tools

Cadence tools

ATPG tooling

Job description

Responsibilities:

• DFT implementation of Scan Logic, IJTAG, MBIST Logic, Logic BIST


• Analysis to improve the testability of Digital design at Block and chip level.


• Implementation of DFT logics for Digital and Mixed Signal IP.


• Perform ATPG pattern generation including SSA /Transition/ Path Delay and IDDQ pattern.


• Perform ATPG verification and simulation playback


• Deliver high quality ATE patterns for production ATE testing


• Provide test pattern support to ATE engineering team for First Proto bring up and failure analysis in the use of ATPG test and scan/debug features

Requirements:

• Bachelor degree or equivalent in Electrical or Computer Engineering


• Familiar with HDL design language


• Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, cshell, Perl)


• Knowledge of ASIC design is a must, and ATE test is a plus


• Strong problem solving skills


• Team player with strong communication skillsCadence tools