Design-for-Test Engineer

Realtek Singapore Private Limited; Singapore; On-site; SGD 70,000 - 100,000; Full time

Job summary

Realtek Singapore Private Limited seeks a skilled Design-For-Test (DFT) Engineer to support design-for-test throughout internal RD groups. You will work with IC Design teams to extend specifications, develop DFT structures (At-speed test, MBIST, test compression, boundary scan), and generate ATPG vectors for fault models and IR analysis.

You will perform functional and ATPG pre- and post-layout simulations while enhancing the scripting environment.

Qualifications

• Experience with DFT concepts and ASIC synthesis.
• Proficiency in TCL or Perl scripting for EDA workflows.
• Excellent written and verbal communication.

Responsibilities

• Collaborate with IC Design teams to define test requirements.
• Develop test plans and design-for-test structures (ATPG, MBIST, boundary scan).
• Create or modify scan constraints and generate ATPG vectors.
• Conduct pre- and post-layout simulations for functional and ATPG tests.
• Enhance internal scripting environments based on needs.

Job description

We are currently seeking a skilled Design-For-Test (DFT) Engineer to join our team at Realtek Singapore. As a DFT Engineer, you will be responsible for providing design for test support to internal RD groups across a wide range of application.

JOB DESCRIPTIONDESCRIPTION

• Collaborate closely with IC Design teams at Realtek.

• Engage with design team to discuss and extend specifications, particularly with respect to test insertion and test pattern generation.

• Develop test plans and implement design-for-test structures (At-speed test, MBIST, test compression, boundary scan), with a strong background in hierarchical DFT flow.

• Create or modify scan constraints.

• Generate ATPG vectors for various fault models and scan fsdb for IR analysis.

• Perform functional and ATPG pre- and post-layout simulations.

• Improve the internal scripting environment based on acquired knowledge.

JOB REQUIREMENTS

• Bachelor's or Master's degree in Electrical Engineering or a related field.

• Proven experience in DFT and ASIC synthesis, with a focus on design-for-test structures.

• Familiarity with industry-standard EDA tools, such as Synopsys, Cadence, or Mentor Graphics.

• Proficiency in scripting languages, such as TCL or Perl.

• Excellent verbal and written communication skills, with the ability to clearly convey technical concepts.